From e3cec4a246a0e3cbaae60c91f946f608f6637f63 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Anton=20P=C3=B6hl?= Date: Thu, 13 Mar 2025 10:52:41 +0100 Subject: [PATCH 1/5] Stm32 usart: make pin modes of cts, tx, rts and de configurable --- embassy-stm32/src/usart/buffered.rs | 28 ++++----- embassy-stm32/src/usart/mod.rs | 90 ++++++++++++++++++++++------- 2 files changed, 84 insertions(+), 34 deletions(-) diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs index b1640b6dc..2dfb99dbc 100644 --- a/embassy-stm32/src/usart/buffered.rs +++ b/embassy-stm32/src/usart/buffered.rs @@ -16,7 +16,7 @@ use super::{ sr, tdr, Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexConfig, HalfDuplexReadback, Info, Instance, Regs, RtsPin, RxPin, TxPin, }; -use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed}; +use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _}; use crate::interrupt::{self, InterruptExt}; use crate::time::Hertz; @@ -217,8 +217,8 @@ impl<'d> BufferedUart<'d> { ) -> Result { Self::new_inner( peri, - new_pin!(rx, AfType::input(config.rx_pull)), - new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(rx, config.rx_af()), + new_pin!(tx, config.tx_af()), None, None, None, @@ -242,10 +242,10 @@ impl<'d> BufferedUart<'d> { ) -> Result { Self::new_inner( peri, - new_pin!(rx, AfType::input(Pull::None)), - new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)), - new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)), - new_pin!(cts, AfType::input(Pull::None)), + new_pin!(rx, config.rx_af()), + new_pin!(tx, config.tx_af()), + new_pin!(rts, config.rts_config.af_type()), + new_pin!(cts, AfType::input(config.cts_pull)), None, tx_buffer, rx_buffer, @@ -266,8 +266,8 @@ impl<'d> BufferedUart<'d> { ) -> Result { Self::new_inner( peri, - new_pin!(rx, AfType::input(Pull::None)), - new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(rx, config.rx_af()), + new_pin!(tx, config.tx_af()), None, None, new_pin!(rts, AfType::input(Pull::None)), // RTS mapped used as DE @@ -290,8 +290,8 @@ impl<'d> BufferedUart<'d> { ) -> Result { Self::new_inner( peri, - new_pin!(rx, AfType::input(Pull::None)), - new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(rx, config.rx_af()), + new_pin!(tx, config.tx_af()), new_pin!(rts, AfType::input(Pull::None)), None, // no CTS None, // no DE @@ -315,11 +315,11 @@ impl<'d> BufferedUart<'d> { ) -> Result { Self::new_inner( peri, - new_pin!(rx, AfType::input(config.rx_pull)), - new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(rx, config.rx_af()), + new_pin!(tx, config.tx_af()), None, None, - new_pin!(de, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(de, config.de_config.af_type()), tx_buffer, rx_buffer, config, diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index 675e90c7f..80a391d41 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs @@ -136,6 +136,40 @@ pub enum HalfDuplexReadback { Readback, } +#[derive(Clone, Copy, PartialEq, Eq, Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +/// Half duplex IO mode +pub enum OutputConfig { + /// Push pull allows for faster baudrates, no internal pullup + PushPull, + #[cfg(not(gpio_v1))] + /// Push pull with internal pull up resistor + PushPullPullUp, + #[cfg(not(gpio_v1))] + /// Push pull with internal pull down resistor + PushPullPullDown, + /// Open drain output using external pull down resistor + OpenDrainExternal, + #[cfg(not(gpio_v1))] + /// Open drain output using internal pull up resistor + OpenDrainInternal, +} + +impl OutputConfig { + const fn af_type(self) -> AfType { + match self { + OutputConfig::PushPull => AfType::output(OutputType::PushPull, Speed::Medium), + #[cfg(not(gpio_v1))] + OutputConfig::PushPullPullUp => AfType::output_pull(OutputType::OpenDrain, Speed::Medium, Pull::Up), + #[cfg(not(gpio_v1))] + OutputConfig::PushPullPullDown => AfType::output_pull(OutputType::OpenDrain, Speed::Medium, Pull::Down), + OutputConfig::OpenDrainExternal => AfType::output(OutputType::OpenDrain, Speed::Medium), + #[cfg(not(gpio_v1))] + OutputConfig::OpenDrainInternal => AfType::output_pull(OutputType::OpenDrain, Speed::Medium, Pull::Up), + } + } +} + #[derive(Clone, Copy, PartialEq, Eq, Debug)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] /// Duplex mode @@ -208,6 +242,18 @@ pub struct Config { /// Set the pull configuration for the RX pin. pub rx_pull: Pull, + /// Set the pull configuration for the CTS pin. + pub cts_pull: Pull, + + /// Set the pin configuration for the TX pin. + pub tx_config: OutputConfig, + + /// Set the pin configuration for the RTS pin. + pub rts_config: OutputConfig, + + /// Set the pin configuration for the DE pin. + pub de_config: OutputConfig, + // private: set by new_half_duplex, not by the user. duplex: Duplex, } @@ -218,13 +264,13 @@ impl Config { if self.swap_rx_tx { return AfType::input(self.rx_pull); }; - AfType::output(OutputType::PushPull, Speed::Medium) + self.tx_config.af_type() } fn rx_af(&self) -> AfType { #[cfg(any(usart_v3, usart_v4))] if self.swap_rx_tx { - return AfType::output(OutputType::PushPull, Speed::Medium); + return self.tx_config.af_type(); }; AfType::input(self.rx_pull) } @@ -248,6 +294,10 @@ impl Default for Config { #[cfg(any(usart_v3, usart_v4))] invert_rx: false, rx_pull: Pull::None, + cts_pull: Pull::None, + tx_config: OutputConfig::PushPull, + rts_config: OutputConfig::PushPull, + de_config: OutputConfig::PushPull, duplex: Duplex::Full, } } @@ -426,7 +476,7 @@ impl<'d> UartTx<'d, Async> { ) -> Result { Self::new_inner( peri, - new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(tx, config.tx_af()), None, new_dma!(tx_dma), config, @@ -443,8 +493,8 @@ impl<'d> UartTx<'d, Async> { ) -> Result { Self::new_inner( peri, - new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)), - new_pin!(cts, AfType::input(Pull::None)), + new_pin!(tx, config.tx_af()), + new_pin!(cts, AfType::input(config.cts_pull)), new_dma!(tx_dma), config, ) @@ -484,7 +534,7 @@ impl<'d> UartTx<'d, Blocking> { ) -> Result { Self::new_inner( peri, - new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(tx, config.tx_af()), None, None, config, @@ -500,8 +550,8 @@ impl<'d> UartTx<'d, Blocking> { ) -> Result { Self::new_inner( peri, - new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)), - new_pin!(cts, AfType::input(config.rx_pull)), + new_pin!(tx, config.tx_af()), + new_pin!(cts, AfType::input(config.cts_pull)), None, config, ) @@ -658,7 +708,7 @@ impl<'d> UartRx<'d, Async> { ) -> Result { Self::new_inner( peri, - new_pin!(rx, AfType::input(config.rx_pull)), + new_pin!(rx, config.rx_af()), None, new_dma!(rx_dma), config, @@ -676,8 +726,8 @@ impl<'d> UartRx<'d, Async> { ) -> Result { Self::new_inner( peri, - new_pin!(rx, AfType::input(config.rx_pull)), - new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(rx, config.rx_af()), + new_pin!(rts, config.rts_config.af_type()), new_dma!(rx_dma), config, ) @@ -912,7 +962,7 @@ impl<'d> UartRx<'d, Blocking> { rx: Peri<'d, impl RxPin>, config: Config, ) -> Result { - Self::new_inner(peri, new_pin!(rx, AfType::input(config.rx_pull)), None, None, config) + Self::new_inner(peri, new_pin!(rx, config.rx_af()), None, None, config) } /// Create a new rx-only UART with a request-to-send pin @@ -924,8 +974,8 @@ impl<'d> UartRx<'d, Blocking> { ) -> Result { Self::new_inner( peri, - new_pin!(rx, AfType::input(config.rx_pull)), - new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(rx, config.rx_af()), + new_pin!(rts, config.rts_config.af_type()), None, config, ) @@ -1141,8 +1191,8 @@ impl<'d> Uart<'d, Async> { peri, new_pin!(rx, config.rx_af()), new_pin!(tx, config.tx_af()), - new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)), - new_pin!(cts, AfType::input(Pull::None)), + new_pin!(rts, config.rts_config.af_type()), + new_pin!(cts, AfType::input(config.cts_pull)), None, new_dma!(tx_dma), new_dma!(rx_dma), @@ -1168,7 +1218,7 @@ impl<'d> Uart<'d, Async> { new_pin!(tx, config.tx_af()), None, None, - new_pin!(de, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(de, config.de_config.af_type()), new_dma!(tx_dma), new_dma!(rx_dma), config, @@ -1308,8 +1358,8 @@ impl<'d> Uart<'d, Blocking> { peri, new_pin!(rx, config.rx_af()), new_pin!(tx, config.tx_af()), - new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)), - new_pin!(cts, AfType::input(Pull::None)), + new_pin!(rts, config.rts_config.af_type()), + new_pin!(cts, AfType::input(config.cts_pull)), None, None, None, @@ -1332,7 +1382,7 @@ impl<'d> Uart<'d, Blocking> { new_pin!(tx, config.tx_af()), None, None, - new_pin!(de, AfType::output(OutputType::PushPull, Speed::Medium)), + new_pin!(de, config.de_config.af_type()), None, None, config, From a544726be4ef66574419e95ee508f2062e9a3da2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Anton=20P=C3=B6hl?= Date: Thu, 13 Mar 2025 11:05:10 +0100 Subject: [PATCH 2/5] Stm32 usart: remove HalfDuplexConfig The pin parameters of usart::Config are used instead. --- embassy-stm32/src/usart/buffered.rs | 8 ++--- embassy-stm32/src/usart/mod.rs | 38 +++------------------ examples/stm32g0/src/bin/onewire_ds18b20.rs | 13 ++++--- 3 files changed, 16 insertions(+), 43 deletions(-) diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs index 2dfb99dbc..57551ff56 100644 --- a/embassy-stm32/src/usart/buffered.rs +++ b/embassy-stm32/src/usart/buffered.rs @@ -13,7 +13,7 @@ use embassy_sync::waitqueue::AtomicWaker; use super::DePin; use super::{ clear_interrupt_flags, configure, half_duplex_set_rx_tx_before_write, rdr, reconfigure, send_break, set_baudrate, - sr, tdr, Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexConfig, HalfDuplexReadback, Info, Instance, Regs, + sr, tdr, Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexReadback, Info, Instance, Regs, RtsPin, RxPin, TxPin, }; use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _}; @@ -346,7 +346,6 @@ impl<'d> BufferedUart<'d> { rx_buffer: &'d mut [u8], mut config: Config, readback: HalfDuplexReadback, - half_duplex: HalfDuplexConfig, ) -> Result { #[cfg(not(any(usart_v1, usart_v2)))] { @@ -357,7 +356,7 @@ impl<'d> BufferedUart<'d> { Self::new_inner( peri, None, - new_pin!(tx, half_duplex.af_type()), + new_pin!(tx, config.tx_af()), None, None, None, @@ -386,14 +385,13 @@ impl<'d> BufferedUart<'d> { rx_buffer: &'d mut [u8], mut config: Config, readback: HalfDuplexReadback, - half_duplex: HalfDuplexConfig, ) -> Result { config.swap_rx_tx = true; config.duplex = Duplex::Half(readback); Self::new_inner( peri, - new_pin!(rx, half_duplex.af_type()), + new_pin!(rx, config.rx_af()), None, None, None, diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index 80a391d41..a6bafc5a7 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs @@ -14,7 +14,7 @@ use embassy_sync::waitqueue::AtomicWaker; use futures_util::future::{select, Either}; use crate::dma::ChannelAndRequest; -use crate::gpio::{self, AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed}; +use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed}; use crate::interrupt::typelevel::Interrupt as _; use crate::interrupt::{self, Interrupt, InterruptExt}; use crate::mode::{Async, Blocking, Mode}; @@ -303,30 +303,6 @@ impl Default for Config { } } -#[derive(Clone, Copy, PartialEq, Eq, Debug)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -/// Half duplex IO mode -pub enum HalfDuplexConfig { - /// Push pull allows for faster baudrates, may require series resistor - PushPull, - /// Open drain output using external pull up resistor - OpenDrainExternal, - #[cfg(not(gpio_v1))] - /// Open drain output using internal pull up resistor - OpenDrainInternal, -} - -impl HalfDuplexConfig { - fn af_type(self) -> gpio::AfType { - match self { - HalfDuplexConfig::PushPull => AfType::output(OutputType::PushPull, Speed::Medium), - HalfDuplexConfig::OpenDrainExternal => AfType::output(OutputType::OpenDrain, Speed::Medium), - #[cfg(not(gpio_v1))] - HalfDuplexConfig::OpenDrainInternal => AfType::output_pull(OutputType::OpenDrain, Speed::Medium, Pull::Up), - } - } -} - /// Serial error #[derive(Debug, Eq, PartialEq, Copy, Clone)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -1245,7 +1221,6 @@ impl<'d> Uart<'d, Async> { rx_dma: Peri<'d, impl RxDma>, mut config: Config, readback: HalfDuplexReadback, - half_duplex: HalfDuplexConfig, ) -> Result { #[cfg(not(any(usart_v1, usart_v2)))] { @@ -1256,7 +1231,7 @@ impl<'d> Uart<'d, Async> { Self::new_inner( peri, None, - new_pin!(tx, half_duplex.af_type()), + new_pin!(tx, config.tx_af()), None, None, None, @@ -1285,7 +1260,6 @@ impl<'d> Uart<'d, Async> { rx_dma: Peri<'d, impl RxDma>, mut config: Config, readback: HalfDuplexReadback, - half_duplex: HalfDuplexConfig, ) -> Result { config.swap_rx_tx = true; config.duplex = Duplex::Half(readback); @@ -1294,7 +1268,7 @@ impl<'d> Uart<'d, Async> { peri, None, None, - new_pin!(rx, half_duplex.af_type()), + new_pin!(rx, config.rx_af()), None, None, new_dma!(tx_dma), @@ -1405,7 +1379,6 @@ impl<'d> Uart<'d, Blocking> { tx: Peri<'d, impl TxPin>, mut config: Config, readback: HalfDuplexReadback, - half_duplex: HalfDuplexConfig, ) -> Result { #[cfg(not(any(usart_v1, usart_v2)))] { @@ -1416,7 +1389,7 @@ impl<'d> Uart<'d, Blocking> { Self::new_inner( peri, None, - new_pin!(tx, half_duplex.af_type()), + new_pin!(tx, config.tx_af()), None, None, None, @@ -1442,7 +1415,6 @@ impl<'d> Uart<'d, Blocking> { rx: Peri<'d, impl RxPin>, mut config: Config, readback: HalfDuplexReadback, - half_duplex: HalfDuplexConfig, ) -> Result { config.swap_rx_tx = true; config.duplex = Duplex::Half(readback); @@ -1451,7 +1423,7 @@ impl<'d> Uart<'d, Blocking> { peri, None, None, - new_pin!(rx, half_duplex.af_type()), + new_pin!(rx, config.rx_af()), None, None, None, diff --git a/examples/stm32g0/src/bin/onewire_ds18b20.rs b/examples/stm32g0/src/bin/onewire_ds18b20.rs index f85cc4ff8..75519bbf2 100644 --- a/examples/stm32g0/src/bin/onewire_ds18b20.rs +++ b/examples/stm32g0/src/bin/onewire_ds18b20.rs @@ -8,7 +8,7 @@ use defmt::*; use embassy_executor::Spawner; use embassy_stm32::mode::Async; use embassy_stm32::usart::{ - BufferedUartRx, BufferedUartTx, Config, ConfigError, HalfDuplexConfig, RingBufferedUartRx, UartTx, + BufferedUartRx, BufferedUartTx, Config, ConfigError, OutputConfig, RingBufferedUartRx, UartTx, }; use embassy_stm32::{bind_interrupts, peripherals, usart}; use embassy_time::{Duration, Timer}; @@ -21,16 +21,18 @@ fn create_onewire(p: embassy_stm32::Peripherals) -> OneWire usart::InterruptHandler; }); + let mut config = Config::default(); + config.tx_config = OutputConfig::OpenDrainExternal; + let usart = Uart::new_half_duplex( p.USART1, p.PA9, Irqs, p.DMA1_CH1, p.DMA1_CH2, - Config::default(), + config, // Enable readback so we can read sensor pulling data low while transmission is in progress usart::HalfDuplexReadback::Readback, - HalfDuplexConfig::OpenDrainExternal, ) .unwrap(); @@ -50,6 +52,8 @@ fn create_onewire(p: embassy_stm32::Peripherals) -> OneWire OneWire Date: Thu, 13 Mar 2025 11:33:11 +0100 Subject: [PATCH 3/5] Format --- embassy-stm32/src/usart/buffered.rs | 4 ++-- embassy-stm32/src/usart/mod.rs | 24 +++--------------------- 2 files changed, 5 insertions(+), 23 deletions(-) diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs index 57551ff56..19dab75a0 100644 --- a/embassy-stm32/src/usart/buffered.rs +++ b/embassy-stm32/src/usart/buffered.rs @@ -13,8 +13,8 @@ use embassy_sync::waitqueue::AtomicWaker; use super::DePin; use super::{ clear_interrupt_flags, configure, half_duplex_set_rx_tx_before_write, rdr, reconfigure, send_break, set_baudrate, - sr, tdr, Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexReadback, Info, Instance, Regs, - RtsPin, RxPin, TxPin, + sr, tdr, Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexReadback, Info, Instance, Regs, RtsPin, RxPin, + TxPin, }; use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _}; use crate::interrupt::{self, InterruptExt}; diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index a6bafc5a7..6c5d3422b 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs @@ -450,13 +450,7 @@ impl<'d> UartTx<'d, Async> { tx_dma: Peri<'d, impl TxDma>, config: Config, ) -> Result { - Self::new_inner( - peri, - new_pin!(tx, config.tx_af()), - None, - new_dma!(tx_dma), - config, - ) + Self::new_inner(peri, new_pin!(tx, config.tx_af()), None, new_dma!(tx_dma), config) } /// Create a new tx-only UART with a clear-to-send pin @@ -508,13 +502,7 @@ impl<'d> UartTx<'d, Blocking> { tx: Peri<'d, impl TxPin>, config: Config, ) -> Result { - Self::new_inner( - peri, - new_pin!(tx, config.tx_af()), - None, - None, - config, - ) + Self::new_inner(peri, new_pin!(tx, config.tx_af()), None, None, config) } /// Create a new blocking tx-only UART with a clear-to-send pin @@ -682,13 +670,7 @@ impl<'d> UartRx<'d, Async> { rx_dma: Peri<'d, impl RxDma>, config: Config, ) -> Result { - Self::new_inner( - peri, - new_pin!(rx, config.rx_af()), - None, - new_dma!(rx_dma), - config, - ) + Self::new_inner(peri, new_pin!(rx, config.rx_af()), None, new_dma!(rx_dma), config) } /// Create a new rx-only UART with a request-to-send pin From de064068995e6f9041d8c4f8e5bd78aabf80fd27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Anton=20P=C3=B6hl?= Date: Sat, 12 Apr 2025 20:56:00 +0200 Subject: [PATCH 4/5] Stm32 usart: Remove meaningless pin configurations --- embassy-stm32/src/usart/mod.rs | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index 6c5d3422b..49f536799 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs @@ -142,12 +142,6 @@ pub enum HalfDuplexReadback { pub enum OutputConfig { /// Push pull allows for faster baudrates, no internal pullup PushPull, - #[cfg(not(gpio_v1))] - /// Push pull with internal pull up resistor - PushPullPullUp, - #[cfg(not(gpio_v1))] - /// Push pull with internal pull down resistor - PushPullPullDown, /// Open drain output using external pull down resistor OpenDrainExternal, #[cfg(not(gpio_v1))] @@ -159,10 +153,6 @@ impl OutputConfig { const fn af_type(self) -> AfType { match self { OutputConfig::PushPull => AfType::output(OutputType::PushPull, Speed::Medium), - #[cfg(not(gpio_v1))] - OutputConfig::PushPullPullUp => AfType::output_pull(OutputType::OpenDrain, Speed::Medium, Pull::Up), - #[cfg(not(gpio_v1))] - OutputConfig::PushPullPullDown => AfType::output_pull(OutputType::OpenDrain, Speed::Medium, Pull::Down), OutputConfig::OpenDrainExternal => AfType::output(OutputType::OpenDrain, Speed::Medium), #[cfg(not(gpio_v1))] OutputConfig::OpenDrainInternal => AfType::output_pull(OutputType::OpenDrain, Speed::Medium, Pull::Up), From 94c208b52a55337658baa894c699c428fc67a449 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Anton=20P=C3=B6hl?= Date: Sun, 13 Apr 2025 20:26:26 +0200 Subject: [PATCH 5/5] Stm32 usart: better names for open drain pin modes --- embassy-stm32/src/usart/mod.rs | 12 ++++++------ examples/stm32g0/src/bin/onewire_ds18b20.rs | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index 49f536799..48f9a84fa 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs @@ -142,20 +142,20 @@ pub enum HalfDuplexReadback { pub enum OutputConfig { /// Push pull allows for faster baudrates, no internal pullup PushPull, - /// Open drain output using external pull down resistor - OpenDrainExternal, + /// Open drain output (external pull up needed) + OpenDrain, #[cfg(not(gpio_v1))] - /// Open drain output using internal pull up resistor - OpenDrainInternal, + /// Open drain output with internal pull up resistor + OpenDrainPullUp, } impl OutputConfig { const fn af_type(self) -> AfType { match self { OutputConfig::PushPull => AfType::output(OutputType::PushPull, Speed::Medium), - OutputConfig::OpenDrainExternal => AfType::output(OutputType::OpenDrain, Speed::Medium), + OutputConfig::OpenDrain => AfType::output(OutputType::OpenDrain, Speed::Medium), #[cfg(not(gpio_v1))] - OutputConfig::OpenDrainInternal => AfType::output_pull(OutputType::OpenDrain, Speed::Medium, Pull::Up), + OutputConfig::OpenDrainPullUp => AfType::output_pull(OutputType::OpenDrain, Speed::Medium, Pull::Up), } } } diff --git a/examples/stm32g0/src/bin/onewire_ds18b20.rs b/examples/stm32g0/src/bin/onewire_ds18b20.rs index 75519bbf2..62f8711a6 100644 --- a/examples/stm32g0/src/bin/onewire_ds18b20.rs +++ b/examples/stm32g0/src/bin/onewire_ds18b20.rs @@ -22,7 +22,7 @@ fn create_onewire(p: embassy_stm32::Peripherals) -> OneWire OneWire