Merge pull request #3667 from williams-one/stm32u5-add-hspi-support
STM32U5: add HSPI support
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
2a06eb2459
@ -1091,6 +1091,27 @@ fn main() {
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(("octospim", "P2_NCS"), quote!(crate::ospi::NSSPin)),
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(("octospim", "P2_CLK"), quote!(crate::ospi::SckPin)),
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(("octospim", "P2_NCLK"), quote!(crate::ospi::NckPin)),
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(("hspi", "IO0"), quote!(crate::hspi::D0Pin)),
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(("hspi", "IO1"), quote!(crate::hspi::D1Pin)),
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(("hspi", "IO2"), quote!(crate::hspi::D2Pin)),
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(("hspi", "IO3"), quote!(crate::hspi::D3Pin)),
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(("hspi", "IO4"), quote!(crate::hspi::D4Pin)),
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(("hspi", "IO5"), quote!(crate::hspi::D5Pin)),
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(("hspi", "IO6"), quote!(crate::hspi::D6Pin)),
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(("hspi", "IO7"), quote!(crate::hspi::D7Pin)),
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(("hspi", "IO8"), quote!(crate::hspi::D8Pin)),
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(("hspi", "IO9"), quote!(crate::hspi::D9Pin)),
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(("hspi", "IO10"), quote!(crate::hspi::D10Pin)),
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(("hspi", "IO11"), quote!(crate::hspi::D11Pin)),
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(("hspi", "IO12"), quote!(crate::hspi::D12Pin)),
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(("hspi", "IO13"), quote!(crate::hspi::D13Pin)),
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(("hspi", "IO14"), quote!(crate::hspi::D14Pin)),
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(("hspi", "IO15"), quote!(crate::hspi::D15Pin)),
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(("hspi", "DQS0"), quote!(crate::hspi::DQS0Pin)),
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(("hspi", "DQS1"), quote!(crate::hspi::DQS1Pin)),
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(("hspi", "NCS"), quote!(crate::hspi::NSSPin)),
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(("hspi", "CLK"), quote!(crate::hspi::SckPin)),
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(("hspi", "NCLK"), quote!(crate::hspi::NckPin)),
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(("tsc", "G1_IO1"), quote!(crate::tsc::G1IO1Pin)),
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(("tsc", "G1_IO2"), quote!(crate::tsc::G1IO2Pin)),
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(("tsc", "G1_IO3"), quote!(crate::tsc::G1IO3Pin)),
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@ -1275,6 +1296,7 @@ fn main() {
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(("sdmmc", "RX"), quote!(crate::sdmmc::SdmmcDma)),
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(("quadspi", "QUADSPI"), quote!(crate::qspi::QuadDma)),
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(("octospi", "OCTOSPI1"), quote!(crate::ospi::OctoDma)),
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(("hspi", "HSPI1"), quote!(crate::hspi::HspiDma)),
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(("dac", "CH1"), quote!(crate::dac::DacDma1)),
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(("dac", "CH2"), quote!(crate::dac::DacDma2)),
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(("timer", "UP"), quote!(crate::timer::UpDma)),
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411
embassy-stm32/src/hspi/enums.rs
Normal file
411
embassy-stm32/src/hspi/enums.rs
Normal file
@ -0,0 +1,411 @@
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//! Enums used in Hspi configuration.
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#[allow(dead_code)]
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#[derive(Copy, Clone, defmt::Format)]
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pub(crate) enum HspiMode {
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IndirectWrite,
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IndirectRead,
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AutoPolling,
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MemoryMapped,
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}
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impl Into<u8> for HspiMode {
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fn into(self) -> u8 {
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match self {
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HspiMode::IndirectWrite => 0b00,
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HspiMode::IndirectRead => 0b01,
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HspiMode::AutoPolling => 0b10,
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HspiMode::MemoryMapped => 0b11,
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}
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}
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}
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/// Hspi lane width
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#[allow(dead_code)]
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#[derive(Copy, Clone, defmt::Format)]
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pub enum HspiWidth {
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/// None
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NONE,
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/// Single lane
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SING,
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/// Dual lanes
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DUAL,
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/// Quad lanes
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QUAD,
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/// Eight lanes
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OCTO,
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/// Sixteen lanes
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HEXADECA,
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}
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impl Into<u8> for HspiWidth {
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fn into(self) -> u8 {
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match self {
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HspiWidth::NONE => 0b00,
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HspiWidth::SING => 0b01,
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HspiWidth::DUAL => 0b10,
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HspiWidth::QUAD => 0b11,
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HspiWidth::OCTO => 0b100,
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HspiWidth::HEXADECA => 0b101,
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}
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}
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}
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/// Flash bank selection
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#[allow(dead_code)]
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#[derive(Copy, Clone, defmt::Format)]
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pub enum FlashSelection {
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/// Bank 1
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Flash1,
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/// Bank 2
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Flash2,
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}
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impl Into<bool> for FlashSelection {
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fn into(self) -> bool {
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match self {
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FlashSelection::Flash1 => false,
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FlashSelection::Flash2 => true,
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}
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}
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}
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/// Wrap Size
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#[allow(dead_code)]
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#[allow(missing_docs)]
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#[derive(Copy, Clone, defmt::Format)]
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pub enum WrapSize {
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None,
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_16Bytes,
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_32Bytes,
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_64Bytes,
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_128Bytes,
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}
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impl Into<u8> for WrapSize {
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fn into(self) -> u8 {
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match self {
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WrapSize::None => 0x00,
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WrapSize::_16Bytes => 0x02,
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WrapSize::_32Bytes => 0x03,
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WrapSize::_64Bytes => 0x04,
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WrapSize::_128Bytes => 0x05,
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}
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}
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}
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/// Memory Type
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#[allow(missing_docs)]
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#[allow(dead_code)]
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#[derive(Copy, Clone, defmt::Format)]
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pub enum MemoryType {
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Micron,
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Macronix,
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Standard,
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MacronixRam,
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HyperBusMemory,
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HyperBusRegister,
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}
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impl Into<u8> for MemoryType {
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fn into(self) -> u8 {
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match self {
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MemoryType::Micron => 0x00,
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MemoryType::Macronix => 0x01,
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MemoryType::Standard => 0x02,
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MemoryType::MacronixRam => 0x03,
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MemoryType::HyperBusMemory => 0x04,
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MemoryType::HyperBusRegister => 0x04,
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}
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}
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}
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/// Hspi memory size.
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#[allow(missing_docs)]
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#[derive(Copy, Clone, defmt::Format)]
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pub enum MemorySize {
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_1KiB,
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_2KiB,
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_4KiB,
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_8KiB,
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_16KiB,
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_32KiB,
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_64KiB,
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_128KiB,
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_256KiB,
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_512KiB,
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_1MiB,
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_2MiB,
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_4MiB,
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_8MiB,
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_16MiB,
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_32MiB,
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_64MiB,
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_128MiB,
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_256MiB,
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_512MiB,
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_1GiB,
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_2GiB,
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_4GiB,
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Other(u8),
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}
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impl Into<u8> for MemorySize {
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fn into(self) -> u8 {
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match self {
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MemorySize::_1KiB => 6,
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MemorySize::_2KiB => 7,
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MemorySize::_4KiB => 8,
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MemorySize::_8KiB => 9,
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MemorySize::_16KiB => 10,
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MemorySize::_32KiB => 11,
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MemorySize::_64KiB => 12,
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MemorySize::_128KiB => 13,
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MemorySize::_256KiB => 14,
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MemorySize::_512KiB => 15,
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MemorySize::_1MiB => 16,
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MemorySize::_2MiB => 17,
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MemorySize::_4MiB => 18,
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MemorySize::_8MiB => 19,
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MemorySize::_16MiB => 20,
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MemorySize::_32MiB => 21,
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MemorySize::_64MiB => 22,
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MemorySize::_128MiB => 23,
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MemorySize::_256MiB => 24,
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MemorySize::_512MiB => 25,
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MemorySize::_1GiB => 26,
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MemorySize::_2GiB => 27,
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MemorySize::_4GiB => 28,
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MemorySize::Other(val) => val,
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}
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}
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}
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/// Hspi Address size
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#[derive(Copy, Clone, defmt::Format)]
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pub enum AddressSize {
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/// 8-bit address
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_8Bit,
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/// 16-bit address
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_16Bit,
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/// 24-bit address
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_24Bit,
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/// 32-bit address
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_32Bit,
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}
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impl Into<u8> for AddressSize {
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fn into(self) -> u8 {
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match self {
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AddressSize::_8Bit => 0b00,
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AddressSize::_16Bit => 0b01,
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AddressSize::_24Bit => 0b10,
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AddressSize::_32Bit => 0b11,
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}
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}
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}
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/// Time the Chip Select line stays high.
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#[allow(missing_docs)]
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#[derive(Copy, Clone, defmt::Format)]
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pub enum ChipSelectHighTime {
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_1Cycle,
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_2Cycle,
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_3Cycle,
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_4Cycle,
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_5Cycle,
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_6Cycle,
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_7Cycle,
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_8Cycle,
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}
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impl Into<u8> for ChipSelectHighTime {
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fn into(self) -> u8 {
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match self {
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ChipSelectHighTime::_1Cycle => 0,
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ChipSelectHighTime::_2Cycle => 1,
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ChipSelectHighTime::_3Cycle => 2,
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ChipSelectHighTime::_4Cycle => 3,
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ChipSelectHighTime::_5Cycle => 4,
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ChipSelectHighTime::_6Cycle => 5,
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ChipSelectHighTime::_7Cycle => 6,
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ChipSelectHighTime::_8Cycle => 7,
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}
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}
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}
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/// FIFO threshold.
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#[allow(missing_docs)]
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#[derive(Copy, Clone, defmt::Format)]
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pub enum FIFOThresholdLevel {
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_1Bytes,
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_2Bytes,
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_3Bytes,
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_4Bytes,
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_5Bytes,
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_6Bytes,
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_7Bytes,
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_8Bytes,
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_9Bytes,
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_10Bytes,
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_11Bytes,
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_12Bytes,
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_13Bytes,
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_14Bytes,
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_15Bytes,
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_16Bytes,
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_17Bytes,
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_18Bytes,
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_19Bytes,
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_20Bytes,
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_21Bytes,
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_22Bytes,
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_23Bytes,
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_24Bytes,
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_25Bytes,
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_26Bytes,
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_27Bytes,
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_28Bytes,
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_29Bytes,
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_30Bytes,
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_31Bytes,
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_32Bytes,
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}
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impl Into<u8> for FIFOThresholdLevel {
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fn into(self) -> u8 {
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match self {
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FIFOThresholdLevel::_1Bytes => 0,
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FIFOThresholdLevel::_2Bytes => 1,
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FIFOThresholdLevel::_3Bytes => 2,
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FIFOThresholdLevel::_4Bytes => 3,
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FIFOThresholdLevel::_5Bytes => 4,
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FIFOThresholdLevel::_6Bytes => 5,
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FIFOThresholdLevel::_7Bytes => 6,
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FIFOThresholdLevel::_8Bytes => 7,
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FIFOThresholdLevel::_9Bytes => 8,
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FIFOThresholdLevel::_10Bytes => 9,
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FIFOThresholdLevel::_11Bytes => 10,
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FIFOThresholdLevel::_12Bytes => 11,
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FIFOThresholdLevel::_13Bytes => 12,
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FIFOThresholdLevel::_14Bytes => 13,
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FIFOThresholdLevel::_15Bytes => 14,
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FIFOThresholdLevel::_16Bytes => 15,
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FIFOThresholdLevel::_17Bytes => 16,
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FIFOThresholdLevel::_18Bytes => 17,
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FIFOThresholdLevel::_19Bytes => 18,
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FIFOThresholdLevel::_20Bytes => 19,
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FIFOThresholdLevel::_21Bytes => 20,
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FIFOThresholdLevel::_22Bytes => 21,
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FIFOThresholdLevel::_23Bytes => 22,
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FIFOThresholdLevel::_24Bytes => 23,
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FIFOThresholdLevel::_25Bytes => 24,
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FIFOThresholdLevel::_26Bytes => 25,
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FIFOThresholdLevel::_27Bytes => 26,
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FIFOThresholdLevel::_28Bytes => 27,
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FIFOThresholdLevel::_29Bytes => 28,
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FIFOThresholdLevel::_30Bytes => 29,
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FIFOThresholdLevel::_31Bytes => 30,
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FIFOThresholdLevel::_32Bytes => 31,
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}
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}
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}
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/// Dummy cycle count
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#[allow(missing_docs)]
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#[derive(Copy, Clone, defmt::Format)]
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pub enum DummyCycles {
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_0,
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_1,
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_2,
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_3,
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_4,
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_5,
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_6,
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_7,
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_8,
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_9,
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_10,
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_11,
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_12,
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_13,
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_14,
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_15,
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_16,
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_17,
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_18,
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_19,
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_20,
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_21,
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_22,
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_23,
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_24,
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_25,
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_26,
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_27,
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_28,
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_29,
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_30,
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_31,
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}
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impl Into<u8> for DummyCycles {
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fn into(self) -> u8 {
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match self {
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DummyCycles::_0 => 0,
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DummyCycles::_1 => 1,
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DummyCycles::_2 => 2,
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DummyCycles::_3 => 3,
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DummyCycles::_4 => 4,
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DummyCycles::_5 => 5,
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DummyCycles::_6 => 6,
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DummyCycles::_7 => 7,
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DummyCycles::_8 => 8,
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DummyCycles::_9 => 9,
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DummyCycles::_10 => 10,
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DummyCycles::_11 => 11,
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DummyCycles::_12 => 12,
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DummyCycles::_13 => 13,
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DummyCycles::_14 => 14,
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DummyCycles::_15 => 15,
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DummyCycles::_16 => 16,
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DummyCycles::_17 => 17,
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DummyCycles::_18 => 18,
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DummyCycles::_19 => 19,
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DummyCycles::_20 => 20,
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DummyCycles::_21 => 21,
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DummyCycles::_22 => 22,
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DummyCycles::_23 => 23,
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DummyCycles::_24 => 24,
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DummyCycles::_25 => 25,
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DummyCycles::_26 => 26,
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DummyCycles::_27 => 27,
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DummyCycles::_28 => 28,
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DummyCycles::_29 => 29,
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DummyCycles::_30 => 30,
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DummyCycles::_31 => 31,
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}
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}
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}
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/// Functional mode
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#[allow(missing_docs)]
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#[allow(dead_code)]
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#[derive(Copy, Clone, defmt::Format)]
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pub enum FunctionalMode {
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IndirectWrite,
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IndirectRead,
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AutoStatusPolling,
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MemoryMapped,
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}
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impl Into<u8> for FunctionalMode {
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fn into(self) -> u8 {
|
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match self {
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FunctionalMode::IndirectWrite => 0x00,
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FunctionalMode::IndirectRead => 0x01,
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FunctionalMode::AutoStatusPolling => 0x02,
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FunctionalMode::MemoryMapped => 0x03,
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}
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}
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}
|
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1008
embassy-stm32/src/hspi/mod.rs
Normal file
1008
embassy-stm32/src/hspi/mod.rs
Normal file
File diff suppressed because it is too large
Load Diff
@ -83,6 +83,8 @@ pub mod hash;
|
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pub mod hrtim;
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#[cfg(hsem)]
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pub mod hsem;
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#[cfg(hspi)]
|
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pub mod hspi;
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#[cfg(i2c)]
|
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pub mod i2c;
|
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#[cfg(any(all(spi_v1, rcc_f4), spi_v3))]
|
||||
|
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@ -52,7 +52,7 @@ pub struct Config {
|
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/// Enables the transaction boundary feature and defines the boundary to release
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/// the chip select
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pub chip_select_boundary: u8,
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/// Enbales the delay block bypass so the sampling is not affected by the delay block
|
||||
/// Enables the delay block bypass so the sampling is not affected by the delay block
|
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pub delay_block_bypass: bool,
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/// Enables communication regulation feature. Chip select is released when the other
|
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/// OctoSpi requests access to the bus
|
||||
|
||||
455
examples/stm32u5/src/bin/hspi_memory_mapped.rs
Normal file
455
examples/stm32u5/src/bin/hspi_memory_mapped.rs
Normal file
@ -0,0 +1,455 @@
|
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#![no_main]
|
||||
#![no_std]
|
||||
|
||||
// Tested on an STM32U5G9J-DK2 demo board using the on-board MX66LM1G45G flash memory
|
||||
// The flash is connected to the HSPI1 port as an OCTA-DTR device
|
||||
//
|
||||
// Use embassy-stm32 feature "stm32u5g9zj" and probe-rs chip "STM32U5G9ZJTxQ"
|
||||
|
||||
use defmt::info;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::hspi::{
|
||||
AddressSize, ChipSelectHighTime, DummyCycles, FIFOThresholdLevel, Hspi, HspiWidth, Instance, MemorySize,
|
||||
MemoryType, TransferConfig, WrapSize,
|
||||
};
|
||||
use embassy_stm32::mode::Async;
|
||||
use embassy_stm32::rcc;
|
||||
use embassy_stm32::time::Hertz;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
info!("Start hspi_memory_mapped");
|
||||
|
||||
// RCC config
|
||||
let mut config = embassy_stm32::Config::default();
|
||||
config.rcc.hse = Some(rcc::Hse {
|
||||
freq: Hertz(16_000_000),
|
||||
mode: rcc::HseMode::Oscillator,
|
||||
});
|
||||
config.rcc.pll1 = Some(rcc::Pll {
|
||||
source: rcc::PllSource::HSE,
|
||||
prediv: rcc::PllPreDiv::DIV1,
|
||||
mul: rcc::PllMul::MUL10,
|
||||
divp: None,
|
||||
divq: None,
|
||||
divr: Some(rcc::PllDiv::DIV1),
|
||||
});
|
||||
config.rcc.sys = rcc::Sysclk::PLL1_R; // 160 Mhz
|
||||
config.rcc.pll2 = Some(rcc::Pll {
|
||||
source: rcc::PllSource::HSE,
|
||||
prediv: rcc::PllPreDiv::DIV4,
|
||||
mul: rcc::PllMul::MUL66,
|
||||
divp: None,
|
||||
divq: Some(rcc::PllDiv::DIV2),
|
||||
divr: None,
|
||||
});
|
||||
config.rcc.mux.hspi1sel = rcc::mux::Hspisel::PLL2_Q; // 132 MHz
|
||||
|
||||
// Initialize peripherals
|
||||
let p = embassy_stm32::init(config);
|
||||
|
||||
let flash_config = embassy_stm32::hspi::Config {
|
||||
fifo_threshold: FIFOThresholdLevel::_4Bytes,
|
||||
memory_type: MemoryType::Macronix,
|
||||
device_size: MemorySize::_1GiB,
|
||||
chip_select_high_time: ChipSelectHighTime::_2Cycle,
|
||||
free_running_clock: false,
|
||||
clock_mode: false,
|
||||
wrap_size: WrapSize::None,
|
||||
clock_prescaler: 0,
|
||||
sample_shifting: false,
|
||||
delay_hold_quarter_cycle: false,
|
||||
chip_select_boundary: 0,
|
||||
delay_block_bypass: false,
|
||||
max_transfer: 0,
|
||||
refresh: 0,
|
||||
};
|
||||
|
||||
let use_dma = true;
|
||||
|
||||
info!("Testing flash in OCTA DTR mode and memory mapped mode");
|
||||
|
||||
let hspi = Hspi::new_octospi(
|
||||
p.HSPI1,
|
||||
p.PI3,
|
||||
p.PH10,
|
||||
p.PH11,
|
||||
p.PH12,
|
||||
p.PH13,
|
||||
p.PH14,
|
||||
p.PH15,
|
||||
p.PI0,
|
||||
p.PI1,
|
||||
p.PH9,
|
||||
p.PI2,
|
||||
p.GPDMA1_CH7,
|
||||
flash_config,
|
||||
);
|
||||
|
||||
let mut flash = OctaDtrFlashMemory::new(hspi).await;
|
||||
|
||||
let flash_id = flash.read_id();
|
||||
info!("FLASH ID: {=[u8]:x}", flash_id);
|
||||
|
||||
let mut rd_buf = [0u8; 16];
|
||||
flash.read_memory(0, &mut rd_buf, use_dma).await;
|
||||
info!("READ BUF: {=[u8]:#X}", rd_buf);
|
||||
|
||||
flash.erase_sector(0).await;
|
||||
flash.read_memory(0, &mut rd_buf, use_dma).await;
|
||||
info!("READ BUF: {=[u8]:#X}", rd_buf);
|
||||
assert_eq!(rd_buf[0], 0xFF);
|
||||
assert_eq!(rd_buf[15], 0xFF);
|
||||
|
||||
let mut wr_buf = [0u8; 16];
|
||||
for i in 0..wr_buf.len() {
|
||||
wr_buf[i] = i as u8;
|
||||
}
|
||||
info!("WRITE BUF: {=[u8]:#X}", wr_buf);
|
||||
flash.write_memory(0, &wr_buf, use_dma).await;
|
||||
flash.read_memory(0, &mut rd_buf, use_dma).await;
|
||||
info!("READ BUF: {=[u8]:#X}", rd_buf);
|
||||
assert_eq!(rd_buf[0], 0x00);
|
||||
assert_eq!(rd_buf[15], 0x0F);
|
||||
|
||||
flash.enable_mm().await;
|
||||
info!("Enabled memory mapped mode");
|
||||
|
||||
let first_u32 = unsafe { *(0xA0000000 as *const u32) };
|
||||
info!("first_u32: 0x{=u32:X}", first_u32);
|
||||
assert_eq!(first_u32, 0x03020100);
|
||||
|
||||
let second_u32 = unsafe { *(0xA0000004 as *const u32) };
|
||||
assert_eq!(second_u32, 0x07060504);
|
||||
info!("second_u32: 0x{=u32:X}", second_u32);
|
||||
|
||||
let first_u8 = unsafe { *(0xA0000000 as *const u8) };
|
||||
assert_eq!(first_u8, 00);
|
||||
info!("first_u8: 0x{=u8:X}", first_u8);
|
||||
|
||||
let second_u8 = unsafe { *(0xA0000001 as *const u8) };
|
||||
assert_eq!(second_u8, 0x01);
|
||||
info!("second_u8: 0x{=u8:X}", second_u8);
|
||||
|
||||
let third_u8 = unsafe { *(0xA0000002 as *const u8) };
|
||||
assert_eq!(third_u8, 0x02);
|
||||
info!("third_u8: 0x{=u8:X}", third_u8);
|
||||
|
||||
let fourth_u8 = unsafe { *(0xA0000003 as *const u8) };
|
||||
assert_eq!(fourth_u8, 0x03);
|
||||
info!("fourth_u8: 0x{=u8:X}", fourth_u8);
|
||||
|
||||
info!("DONE");
|
||||
}
|
||||
|
||||
// Custom implementation for MX66UW1G45G NOR flash memory from Macronix.
|
||||
// Chip commands are hardcoded as they depend on the chip used.
|
||||
// This implementation enables Octa I/O (OPI) and Double Transfer Rate (DTR)
|
||||
|
||||
pub struct OctaDtrFlashMemory<'d, I: Instance> {
|
||||
hspi: Hspi<'d, I, Async>,
|
||||
}
|
||||
|
||||
impl<'d, I: Instance> OctaDtrFlashMemory<'d, I> {
|
||||
const MEMORY_PAGE_SIZE: usize = 256;
|
||||
|
||||
const CMD_READ_OCTA_DTR: u16 = 0xEE11;
|
||||
const CMD_PAGE_PROGRAM_OCTA_DTR: u16 = 0x12ED;
|
||||
|
||||
const CMD_READ_ID_OCTA_DTR: u16 = 0x9F60;
|
||||
|
||||
const CMD_RESET_ENABLE: u8 = 0x66;
|
||||
const CMD_RESET_ENABLE_OCTA_DTR: u16 = 0x6699;
|
||||
const CMD_RESET: u8 = 0x99;
|
||||
const CMD_RESET_OCTA_DTR: u16 = 0x9966;
|
||||
|
||||
const CMD_WRITE_ENABLE: u8 = 0x06;
|
||||
const CMD_WRITE_ENABLE_OCTA_DTR: u16 = 0x06F9;
|
||||
|
||||
const CMD_SECTOR_ERASE_OCTA_DTR: u16 = 0x21DE;
|
||||
const CMD_BLOCK_ERASE_OCTA_DTR: u16 = 0xDC23;
|
||||
|
||||
const CMD_READ_SR: u8 = 0x05;
|
||||
const CMD_READ_SR_OCTA_DTR: u16 = 0x05FA;
|
||||
|
||||
const CMD_READ_CR2: u8 = 0x71;
|
||||
const CMD_WRITE_CR2: u8 = 0x72;
|
||||
|
||||
const CR2_REG1_ADDR: u32 = 0x00000000;
|
||||
const CR2_OCTA_DTR: u8 = 0x02;
|
||||
|
||||
const CR2_REG3_ADDR: u32 = 0x00000300;
|
||||
const CR2_DC_6_CYCLES: u8 = 0x07;
|
||||
|
||||
pub async fn new(hspi: Hspi<'d, I, Async>) -> Self {
|
||||
let mut memory = Self { hspi };
|
||||
|
||||
memory.reset_memory().await;
|
||||
memory.enable_octa_dtr().await;
|
||||
memory
|
||||
}
|
||||
|
||||
async fn enable_octa_dtr(&mut self) {
|
||||
self.write_enable_spi().await;
|
||||
self.write_cr2_spi(Self::CR2_REG3_ADDR, Self::CR2_DC_6_CYCLES);
|
||||
self.write_enable_spi().await;
|
||||
self.write_cr2_spi(Self::CR2_REG1_ADDR, Self::CR2_OCTA_DTR);
|
||||
}
|
||||
|
||||
pub async fn enable_mm(&mut self) {
|
||||
let read_config = TransferConfig {
|
||||
iwidth: HspiWidth::OCTO,
|
||||
instruction: Some(Self::CMD_READ_OCTA_DTR as u32),
|
||||
isize: AddressSize::_16Bit,
|
||||
idtr: true,
|
||||
adwidth: HspiWidth::OCTO,
|
||||
adsize: AddressSize::_32Bit,
|
||||
addtr: true,
|
||||
dwidth: HspiWidth::OCTO,
|
||||
ddtr: true,
|
||||
dummy: DummyCycles::_6,
|
||||
..Default::default()
|
||||
};
|
||||
|
||||
let write_config = TransferConfig {
|
||||
iwidth: HspiWidth::OCTO,
|
||||
isize: AddressSize::_16Bit,
|
||||
idtr: true,
|
||||
adwidth: HspiWidth::OCTO,
|
||||
adsize: AddressSize::_32Bit,
|
||||
addtr: true,
|
||||
dwidth: HspiWidth::OCTO,
|
||||
ddtr: true,
|
||||
..Default::default()
|
||||
};
|
||||
self.hspi.enable_memory_mapped_mode(read_config, write_config).unwrap();
|
||||
}
|
||||
|
||||
async fn exec_command_spi(&mut self, cmd: u8) {
|
||||
let transaction = TransferConfig {
|
||||
iwidth: HspiWidth::SING,
|
||||
instruction: Some(cmd as u32),
|
||||
..Default::default()
|
||||
};
|
||||
info!("Excuting command: 0x{:X}", transaction.instruction.unwrap());
|
||||
self.hspi.blocking_command(&transaction).unwrap();
|
||||
}
|
||||
|
||||
async fn exec_command_octa_dtr(&mut self, cmd: u16) {
|
||||
let transaction = TransferConfig {
|
||||
iwidth: HspiWidth::OCTO,
|
||||
instruction: Some(cmd as u32),
|
||||
isize: AddressSize::_16Bit,
|
||||
idtr: true,
|
||||
..Default::default()
|
||||
};
|
||||
info!("Excuting command: 0x{:X}", transaction.instruction.unwrap());
|
||||
self.hspi.blocking_command(&transaction).unwrap();
|
||||
}
|
||||
|
||||
fn wait_write_finish_spi(&mut self) {
|
||||
while (self.read_sr_spi() & 0x01) != 0 {}
|
||||
}
|
||||
|
||||
fn wait_write_finish_octa_dtr(&mut self) {
|
||||
while (self.read_sr_octa_dtr() & 0x01) != 0 {}
|
||||
}
|
||||
|
||||
pub async fn reset_memory(&mut self) {
|
||||
// servono entrambi i comandi?
|
||||
self.exec_command_octa_dtr(Self::CMD_RESET_ENABLE_OCTA_DTR).await;
|
||||
self.exec_command_octa_dtr(Self::CMD_RESET_OCTA_DTR).await;
|
||||
self.exec_command_spi(Self::CMD_RESET_ENABLE).await;
|
||||
self.exec_command_spi(Self::CMD_RESET).await;
|
||||
self.wait_write_finish_spi();
|
||||
}
|
||||
|
||||
async fn write_enable_spi(&mut self) {
|
||||
self.exec_command_spi(Self::CMD_WRITE_ENABLE).await;
|
||||
}
|
||||
|
||||
async fn write_enable_octa_dtr(&mut self) {
|
||||
self.exec_command_octa_dtr(Self::CMD_WRITE_ENABLE_OCTA_DTR).await;
|
||||
}
|
||||
|
||||
pub fn read_id(&mut self) -> [u8; 3] {
|
||||
let mut buffer = [0; 6];
|
||||
let transaction: TransferConfig = TransferConfig {
|
||||
iwidth: HspiWidth::OCTO,
|
||||
instruction: Some(Self::CMD_READ_ID_OCTA_DTR as u32),
|
||||
isize: AddressSize::_16Bit,
|
||||
idtr: true,
|
||||
adwidth: HspiWidth::OCTO,
|
||||
address: Some(0),
|
||||
adsize: AddressSize::_32Bit,
|
||||
addtr: true,
|
||||
dwidth: HspiWidth::OCTO,
|
||||
ddtr: true,
|
||||
dummy: DummyCycles::_5,
|
||||
..Default::default()
|
||||
};
|
||||
info!("Reading flash id: 0x{:X}", transaction.instruction.unwrap());
|
||||
self.hspi.blocking_read(&mut buffer, transaction).unwrap();
|
||||
[buffer[0], buffer[2], buffer[4]]
|
||||
}
|
||||
|
||||
pub async fn read_memory(&mut self, addr: u32, buffer: &mut [u8], use_dma: bool) {
|
||||
let transaction = TransferConfig {
|
||||
iwidth: HspiWidth::OCTO,
|
||||
instruction: Some(Self::CMD_READ_OCTA_DTR as u32),
|
||||
isize: AddressSize::_16Bit,
|
||||
idtr: true,
|
||||
adwidth: HspiWidth::OCTO,
|
||||
address: Some(addr),
|
||||
adsize: AddressSize::_32Bit,
|
||||
addtr: true,
|
||||
dwidth: HspiWidth::OCTO,
|
||||
ddtr: true,
|
||||
dummy: DummyCycles::_6,
|
||||
..Default::default()
|
||||
};
|
||||
if use_dma {
|
||||
self.hspi.read(buffer, transaction).await.unwrap();
|
||||
} else {
|
||||
self.hspi.blocking_read(buffer, transaction).unwrap();
|
||||
}
|
||||
}
|
||||
|
||||
async fn perform_erase_octa_dtr(&mut self, addr: u32, cmd: u16) {
|
||||
let transaction = TransferConfig {
|
||||
iwidth: HspiWidth::OCTO,
|
||||
instruction: Some(cmd as u32),
|
||||
isize: AddressSize::_16Bit,
|
||||
idtr: true,
|
||||
adwidth: HspiWidth::OCTO,
|
||||
address: Some(addr),
|
||||
adsize: AddressSize::_32Bit,
|
||||
addtr: true,
|
||||
..Default::default()
|
||||
};
|
||||
self.write_enable_octa_dtr().await;
|
||||
self.hspi.blocking_command(&transaction).unwrap();
|
||||
self.wait_write_finish_octa_dtr();
|
||||
}
|
||||
|
||||
pub async fn erase_sector(&mut self, addr: u32) {
|
||||
info!("Erasing 4K sector at address: 0x{:X}", addr);
|
||||
self.perform_erase_octa_dtr(addr, Self::CMD_SECTOR_ERASE_OCTA_DTR).await;
|
||||
}
|
||||
|
||||
pub async fn erase_block(&mut self, addr: u32) {
|
||||
info!("Erasing 64K block at address: 0x{:X}", addr);
|
||||
self.perform_erase_octa_dtr(addr, Self::CMD_BLOCK_ERASE_OCTA_DTR).await;
|
||||
}
|
||||
|
||||
async fn write_page_octa_dtr(&mut self, addr: u32, buffer: &[u8], len: usize, use_dma: bool) {
|
||||
assert!(
|
||||
(len as u32 + (addr & 0x000000ff)) <= Self::MEMORY_PAGE_SIZE as u32,
|
||||
"write_page(): page write length exceeds page boundary (len = {}, addr = {:X}",
|
||||
len,
|
||||
addr
|
||||
);
|
||||
|
||||
let transaction = TransferConfig {
|
||||
iwidth: HspiWidth::OCTO,
|
||||
instruction: Some(Self::CMD_PAGE_PROGRAM_OCTA_DTR as u32),
|
||||
isize: AddressSize::_16Bit,
|
||||
idtr: true,
|
||||
adwidth: HspiWidth::OCTO,
|
||||
address: Some(addr),
|
||||
adsize: AddressSize::_32Bit,
|
||||
addtr: true,
|
||||
dwidth: HspiWidth::OCTO,
|
||||
ddtr: true,
|
||||
..Default::default()
|
||||
};
|
||||
self.write_enable_octa_dtr().await;
|
||||
if use_dma {
|
||||
self.hspi.write(buffer, transaction).await.unwrap();
|
||||
} else {
|
||||
self.hspi.blocking_write(buffer, transaction).unwrap();
|
||||
}
|
||||
self.wait_write_finish_octa_dtr();
|
||||
}
|
||||
|
||||
pub async fn write_memory(&mut self, addr: u32, buffer: &[u8], use_dma: bool) {
|
||||
let mut left = buffer.len();
|
||||
let mut place = addr;
|
||||
let mut chunk_start = 0;
|
||||
|
||||
while left > 0 {
|
||||
let max_chunk_size = Self::MEMORY_PAGE_SIZE - (place & 0x000000ff) as usize;
|
||||
let chunk_size = if left >= max_chunk_size { max_chunk_size } else { left };
|
||||
let chunk = &buffer[chunk_start..(chunk_start + chunk_size)];
|
||||
self.write_page_octa_dtr(place, chunk, chunk_size, use_dma).await;
|
||||
place += chunk_size as u32;
|
||||
left -= chunk_size;
|
||||
chunk_start += chunk_size;
|
||||
}
|
||||
}
|
||||
|
||||
pub fn read_sr_spi(&mut self) -> u8 {
|
||||
let mut buffer = [0; 1];
|
||||
let transaction: TransferConfig = TransferConfig {
|
||||
iwidth: HspiWidth::SING,
|
||||
instruction: Some(Self::CMD_READ_SR as u32),
|
||||
dwidth: HspiWidth::SING,
|
||||
..Default::default()
|
||||
};
|
||||
self.hspi.blocking_read(&mut buffer, transaction).unwrap();
|
||||
// info!("Read MX66LM1G45G SR register: 0x{:x}", buffer[0]);
|
||||
buffer[0]
|
||||
}
|
||||
|
||||
pub fn read_sr_octa_dtr(&mut self) -> u8 {
|
||||
let mut buffer = [0; 2];
|
||||
let transaction: TransferConfig = TransferConfig {
|
||||
iwidth: HspiWidth::OCTO,
|
||||
instruction: Some(Self::CMD_READ_SR_OCTA_DTR as u32),
|
||||
isize: AddressSize::_16Bit,
|
||||
idtr: true,
|
||||
adwidth: HspiWidth::OCTO,
|
||||
address: Some(0),
|
||||
adsize: AddressSize::_32Bit,
|
||||
addtr: true,
|
||||
dwidth: HspiWidth::OCTO,
|
||||
ddtr: true,
|
||||
dummy: DummyCycles::_5,
|
||||
..Default::default()
|
||||
};
|
||||
self.hspi.blocking_read(&mut buffer, transaction).unwrap();
|
||||
// info!("Read MX66LM1G45G SR register: 0x{:x}", buffer[0]);
|
||||
buffer[0]
|
||||
}
|
||||
|
||||
pub fn read_cr2_spi(&mut self, addr: u32) -> u8 {
|
||||
let mut buffer = [0; 1];
|
||||
let transaction: TransferConfig = TransferConfig {
|
||||
iwidth: HspiWidth::SING,
|
||||
instruction: Some(Self::CMD_READ_CR2 as u32),
|
||||
adwidth: HspiWidth::SING,
|
||||
address: Some(addr),
|
||||
adsize: AddressSize::_32Bit,
|
||||
dwidth: HspiWidth::SING,
|
||||
..Default::default()
|
||||
};
|
||||
self.hspi.blocking_read(&mut buffer, transaction).unwrap();
|
||||
// info!("Read MX66LM1G45G CR2[0x{:X}] register: 0x{:x}", addr, buffer[0]);
|
||||
buffer[0]
|
||||
}
|
||||
|
||||
pub fn write_cr2_spi(&mut self, addr: u32, value: u8) {
|
||||
let buffer = [value; 1];
|
||||
let transaction: TransferConfig = TransferConfig {
|
||||
iwidth: HspiWidth::SING,
|
||||
instruction: Some(Self::CMD_WRITE_CR2 as u32),
|
||||
adwidth: HspiWidth::SING,
|
||||
address: Some(addr),
|
||||
adsize: AddressSize::_32Bit,
|
||||
dwidth: HspiWidth::SING,
|
||||
..Default::default()
|
||||
};
|
||||
self.hspi.blocking_write(&buffer, transaction).unwrap();
|
||||
}
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user