Dario Nieuwenhuis
GitHub
commit
282f00e705
116
embassy-nrf-examples/src/bin/spim.rs
Normal file
116
embassy-nrf-examples/src/bin/spim.rs
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@ -0,0 +1,116 @@
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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#[path = "../example_common.rs"]
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mod example_common;
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use example_common::*;
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use cortex_m_rt::entry;
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use defmt::panic;
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use embassy::executor::{task, Executor};
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use embassy::util::Forever;
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use embedded_hal::digital::v2::*;
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use futures::pin_mut;
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use nrf52840_hal::clocks;
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use nrf52840_hal::gpio;
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use embassy_nrf::{interrupt, pac, rtc, spim};
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#[task]
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async fn run() {
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info!("running!");
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let p = unsafe { embassy_nrf::pac::Peripherals::steal() };
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let p0 = gpio::p0::Parts::new(p.P0);
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let pins = spim::Pins {
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sck: p0.p0_29.into_push_pull_output(gpio::Level::Low).degrade(),
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miso: Some(p0.p0_28.into_floating_input().degrade()),
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mosi: Some(p0.p0_30.into_push_pull_output(gpio::Level::Low).degrade()),
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};
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let config = spim::Config {
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pins,
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frequency: spim::Frequency::M16,
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mode: spim::MODE_0,
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orc: 0x00,
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};
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let mut ncs = p0.p0_31.into_push_pull_output(gpio::Level::High);
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let spim = spim::Spim::new(p.SPIM3, interrupt::take!(SPIM3), config);
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pin_mut!(spim);
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// Example on how to talk to an ENC28J60 chip
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// softreset
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cortex_m::asm::delay(10);
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ncs.set_low().unwrap();
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cortex_m::asm::delay(5);
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let tx = [0xFF];
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unwrap!(spim.as_mut().send_receive(&tx, &mut []).await);
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cortex_m::asm::delay(10);
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ncs.set_high().unwrap();
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cortex_m::asm::delay(100000);
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let mut rx = [0; 2];
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// read ESTAT
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cortex_m::asm::delay(5000);
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ncs.set_low().unwrap();
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cortex_m::asm::delay(5000);
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let tx = [0b000_11101, 0];
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unwrap!(spim.as_mut().send_receive(&tx, &mut rx).await);
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cortex_m::asm::delay(5000);
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ncs.set_high().unwrap();
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info!("estat: {=[?]}", rx);
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// Switch to bank 3
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cortex_m::asm::delay(10);
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ncs.set_low().unwrap();
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cortex_m::asm::delay(5);
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let tx = [0b100_11111, 0b11];
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unwrap!(spim.as_mut().send_receive(&tx, &mut rx).await);
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cortex_m::asm::delay(10);
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ncs.set_high().unwrap();
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// read EREVID
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cortex_m::asm::delay(10);
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ncs.set_low().unwrap();
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cortex_m::asm::delay(5);
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let tx = [0b000_10010, 0];
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unwrap!(spim.as_mut().send_receive(&tx, &mut rx).await);
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cortex_m::asm::delay(10);
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ncs.set_high().unwrap();
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info!("erevid: {=[?]}", rx);
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}
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static RTC: Forever<rtc::RTC<pac::RTC1>> = Forever::new();
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static ALARM: Forever<rtc::Alarm<pac::RTC1>> = Forever::new();
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static EXECUTOR: Forever<Executor> = Forever::new();
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#[entry]
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fn main() -> ! {
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info!("Hello World!");
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let p = unwrap!(embassy_nrf::pac::Peripherals::take());
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clocks::Clocks::new(p.CLOCK)
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.enable_ext_hfosc()
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.set_lfclk_src_external(clocks::LfOscConfiguration::NoExternalNoBypass)
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.start_lfclk();
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let rtc = RTC.put(rtc::RTC::new(p.RTC1, interrupt::take!(RTC1)));
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rtc.start();
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unsafe { embassy::time::set_clock(rtc) };
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let alarm = ALARM.put(rtc.alarm0());
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let executor = EXECUTOR.put(Executor::new());
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executor.set_alarm(alarm);
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executor.run(|spawner| {
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unwrap!(spawner.spawn(run()));
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});
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}
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@ -49,6 +49,45 @@ pub use nrf52833_hal as hal;
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#[cfg(feature = "52840")]
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pub use nrf52840_hal as hal;
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/// Length of Nordic EasyDMA differs for MCUs
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#[cfg(any(
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feature = "52810",
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feature = "52811",
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feature = "52832",
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feature = "51"
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))]
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pub mod target_constants {
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// NRF52832 8 bits1..0xFF
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pub const EASY_DMA_SIZE: usize = 255;
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// Easy DMA can only read from data ram
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pub const SRAM_LOWER: usize = 0x2000_0000;
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pub const SRAM_UPPER: usize = 0x3000_0000;
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}
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#[cfg(any(feature = "52840", feature = "52833", feature = "9160"))]
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pub mod target_constants {
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// NRF52840 and NRF9160 16 bits 1..0xFFFF
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pub const EASY_DMA_SIZE: usize = 65535;
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// Limits for Easy DMA - it can only read from data ram
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pub const SRAM_LOWER: usize = 0x2000_0000;
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pub const SRAM_UPPER: usize = 0x3000_0000;
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}
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/// Does this slice reside entirely within RAM?
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pub(crate) fn slice_in_ram(slice: &[u8]) -> bool {
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let ptr = slice.as_ptr() as usize;
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ptr >= target_constants::SRAM_LOWER && (ptr + slice.len()) < target_constants::SRAM_UPPER
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}
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/// Return an error if slice is not in RAM.
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#[cfg(not(feature = "51"))]
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pub(crate) fn slice_in_ram_or<T>(slice: &[u8], err: T) -> Result<(), T> {
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if slice.len() == 0 || slice_in_ram(slice) {
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Ok(())
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} else {
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Err(err)
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}
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}
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// This mod MUST go first, so that the others see its macros.
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pub(crate) mod fmt;
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pub(crate) mod util;
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@ -59,4 +98,5 @@ pub mod interrupt;
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#[cfg(feature = "52840")]
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pub mod qspi;
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pub mod rtc;
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pub mod spim;
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pub mod uarte;
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272
embassy-nrf/src/spim.rs
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272
embassy-nrf/src/spim.rs
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@ -0,0 +1,272 @@
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use core::future::Future;
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use core::pin::Pin;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy::util::WakerRegistration;
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use futures::future::poll_fn;
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use crate::hal::gpio::Port as GpioPort;
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use crate::interrupt::{self, Interrupt};
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use crate::util::peripheral::{PeripheralMutex, PeripheralState};
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use crate::{pac, slice_in_ram_or};
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pub use crate::hal::spim::{
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Frequency, Mode, Phase, Pins, Polarity, MODE_0, MODE_1, MODE_2, MODE_3,
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};
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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TxBufferTooLong,
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RxBufferTooLong,
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/// EasyDMA can only read from data memory, read only buffers in flash will fail.
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DMABufferNotInDataMemory,
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}
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struct State<T: Instance> {
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spim: T,
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waker: WakerRegistration,
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}
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pub struct Spim<T: Instance> {
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inner: PeripheralMutex<State<T>>,
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}
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#[cfg(any(feature = "52833", feature = "52840"))]
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fn port_bit(port: GpioPort) -> bool {
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match port {
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GpioPort::Port0 => false,
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GpioPort::Port1 => true,
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}
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}
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pub struct Config {
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pub pins: Pins,
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pub frequency: Frequency,
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pub mode: Mode,
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pub orc: u8,
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}
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impl<T: Instance> Spim<T> {
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pub fn new(mut spim: T, irq: T::Interrupt, config: Config) -> Self {
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let r = spim.regs();
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// Select pins.
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r.psel.sck.write(|w| {
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let w = unsafe { w.pin().bits(config.pins.sck.pin()) };
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#[cfg(any(feature = "52833", feature = "52840"))]
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let w = w.port().bit(port_bit(config.pins.sck.port()));
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w.connect().connected()
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});
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match config.pins.mosi {
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Some(mosi) => r.psel.mosi.write(|w| {
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let w = unsafe { w.pin().bits(mosi.pin()) };
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#[cfg(any(feature = "52833", feature = "52840"))]
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let w = w.port().bit(port_bit(mosi.port()));
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w.connect().connected()
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}),
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None => r.psel.mosi.write(|w| w.connect().disconnected()),
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}
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match config.pins.miso {
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Some(miso) => r.psel.miso.write(|w| {
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let w = unsafe { w.pin().bits(miso.pin()) };
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#[cfg(any(feature = "52833", feature = "52840"))]
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let w = w.port().bit(port_bit(miso.port()));
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w.connect().connected()
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}),
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None => r.psel.miso.write(|w| w.connect().disconnected()),
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}
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// Enable SPIM instance.
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r.enable.write(|w| w.enable().enabled());
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// Configure mode.
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let mode = config.mode;
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r.config.write(|w| {
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// Can't match on `mode` due to embedded-hal, see https://github.com/rust-embedded/embedded-hal/pull/126
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if mode == MODE_0 {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().leading();
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} else if mode == MODE_1 {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().trailing();
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} else if mode == MODE_2 {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().leading();
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} else {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().trailing();
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}
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w
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});
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// Configure frequency.
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let frequency = config.frequency;
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r.frequency.write(|w| w.frequency().variant(frequency));
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// Set over-read character
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let orc = config.orc;
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r.orc.write(|w|
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// The ORC field is 8 bits long, so any u8 is a valid value to write.
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unsafe { w.orc().bits(orc) });
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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Self {
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inner: PeripheralMutex::new(
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State {
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spim,
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waker: WakerRegistration::new(),
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},
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irq,
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),
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}
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}
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fn inner(self: Pin<&mut Self>) -> Pin<&mut PeripheralMutex<State<T>>> {
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unsafe { Pin::new_unchecked(&mut self.get_unchecked_mut().inner) }
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}
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pub fn free(self: Pin<&mut Self>) -> (T, T::Interrupt) {
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let (state, irq) = self.inner().free();
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(state.spim, irq)
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}
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pub fn send_receive<'a>(
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mut self: Pin<&'a mut Self>,
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tx: &'a [u8],
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rx: &'a mut [u8],
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) -> impl Future<Output = Result<(), Error>> + 'a {
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async move {
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slice_in_ram_or(tx, Error::DMABufferNotInDataMemory)?;
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slice_in_ram_or(rx, Error::DMABufferNotInDataMemory)?;
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self.as_mut().inner().with(|s, _irq| {
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// before any DMA action has started.
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compiler_fence(Ordering::SeqCst);
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let r = s.spim.regs();
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// Set up the DMA write.
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r.txd
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.ptr
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.write(|w| unsafe { w.ptr().bits(tx.as_ptr() as u32) });
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r.txd
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.maxcnt
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.write(|w| unsafe { w.maxcnt().bits(tx.len() as _) });
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// Set up the DMA read.
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r.rxd
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.ptr
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.write(|w| unsafe { w.ptr().bits(rx.as_mut_ptr() as u32) });
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r.rxd
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.maxcnt
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.write(|w| unsafe { w.maxcnt().bits(rx.len() as _) });
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// Reset and enable the event
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r.events_end.reset();
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r.intenset.write(|w| w.end().set());
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// Start SPI transaction.
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r.tasks_start.write(|w| unsafe { w.bits(1) });
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// after all possible DMA actions have completed.
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compiler_fence(Ordering::SeqCst);
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});
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// Wait for 'end' event.
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poll_fn(|cx| {
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self.as_mut().inner().with(|s, _irq| {
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let r = s.spim.regs();
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if r.events_end.read().bits() != 0 {
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return Poll::Ready(());
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}
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s.waker.register(cx.waker());
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Poll::Pending
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})
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})
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.await;
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Ok(())
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}
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}
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}
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impl<U: Instance> PeripheralState for State<U> {
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type Interrupt = U::Interrupt;
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fn on_interrupt(&mut self) {
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if self.spim.regs().events_end.read().bits() != 0 {
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self.spim.regs().intenclr.write(|w| w.end().clear());
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self.waker.wake()
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}
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}
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}
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mod sealed {
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pub trait Instance {}
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}
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pub trait Instance: sealed::Instance {
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type Interrupt: Interrupt;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock;
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}
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impl sealed::Instance for pac::SPIM0 {}
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impl Instance for pac::SPIM0 {
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#[cfg(feature = "52810")]
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type Interrupt = interrupt::SPIM0_SPIS0_SPI0;
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#[cfg(not(feature = "52810"))]
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type Interrupt = interrupt::SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock {
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self
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}
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}
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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impl sealed::Instance for pac::SPIM1 {}
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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impl Instance for pac::SPIM1 {
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type Interrupt = interrupt::SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock {
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self
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}
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}
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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impl sealed::Instance for pac::SPIM2 {}
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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impl Instance for pac::SPIM2 {
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type Interrupt = interrupt::SPIM2_SPIS2_SPI2;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock {
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self
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}
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}
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#[cfg(any(feature = "52833", feature = "52840"))]
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impl sealed::Instance for pac::SPIM3 {}
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#[cfg(any(feature = "52833", feature = "52840"))]
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impl Instance for pac::SPIM3 {
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type Interrupt = interrupt::SPIM3;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock {
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self
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}
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}
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impl<T: sealed::Instance> sealed::Instance for &mut T {}
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impl<T: Instance> Instance for &mut T {
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type Interrupt = T::Interrupt;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock {
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T::regs(*self)
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}
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}
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