Merge pull request #3280 from elagil/feat_spdifrx_driver
Support for STM32 SPDIFRX
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
227e073fca
@ -1220,6 +1220,17 @@ fn main() {
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impl_dac_pin!( #peri, #pin_name, #ch);
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})
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}
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if regs.kind == "spdifrx" {
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let peri = format_ident!("{}", p.name);
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let pin_name = format_ident!("{}", pin.pin);
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let af = pin.af.unwrap_or(0);
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let sel: u8 = pin.signal.strip_prefix("IN").unwrap().parse().unwrap();
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g.extend(quote! {
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impl_spdifrx_pin!( #peri, #pin_name, #af, #sel);
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})
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}
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}
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}
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}
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@ -1244,6 +1255,7 @@ fn main() {
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(("sai", "B"), quote!(crate::sai::Dma<B>)),
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(("spi", "RX"), quote!(crate::spi::RxDma)),
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(("spi", "TX"), quote!(crate::spi::TxDma)),
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(("spdifrx", "RX"), quote!(crate::spdifrx::Dma)),
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(("i2c", "RX"), quote!(crate::i2c::RxDma)),
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(("i2c", "TX"), quote!(crate::i2c::TxDma)),
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(("dcmi", "DCMI"), quote!(crate::dcmi::FrameDma)),
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@ -107,6 +107,8 @@ pub mod rtc;
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pub mod sai;
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#[cfg(sdmmc)]
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pub mod sdmmc;
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#[cfg(spdifrx)]
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pub mod spdifrx;
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#[cfg(spi)]
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pub mod spi;
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#[cfg(tsc)]
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336
embassy-stm32/src/spdifrx/mod.rs
Normal file
336
embassy-stm32/src/spdifrx/mod.rs
Normal file
@ -0,0 +1,336 @@
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//! S/PDIF receiver
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#![macro_use]
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#![cfg_attr(gpdma, allow(unused))]
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use core::marker::PhantomData;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use crate::dma::ringbuffer::Error as RingbufferError;
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pub use crate::dma::word;
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#[cfg(not(gpdma))]
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use crate::dma::ReadableRingBuffer;
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use crate::dma::{Channel, TransferOptions};
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use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _};
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use crate::interrupt::typelevel::Interrupt;
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use crate::pac::spdifrx::Spdifrx as Regs;
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use crate::rcc::{RccInfo, SealedRccPeripheral};
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use crate::{interrupt, peripherals, Peripheral};
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/// Possible S/PDIF preamble types.
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#[allow(dead_code)]
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#[repr(u8)]
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enum PreambleType {
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Unused = 0x00,
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/// The preamble changes to preamble “B” once every 192 frames to identify the start of the block structure used to
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/// organize the channel status and user information.
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B = 0x01,
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/// The first sub-frame (left or “A” channel in stereophonic operation and primary channel in monophonic operation)
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/// normally starts with preamble “M”
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M = 0x02,
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/// The second sub-frame (right or “B” channel in stereophonic operation and secondary channel in monophonic
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/// operation) always starts with preamble “W”.
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W = 0x03,
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}
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macro_rules! new_spdifrx_pin {
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($name:ident, $af_type:expr) => {{
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let pin = $name.into_ref();
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let input_sel = pin.input_sel();
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pin.set_as_af(pin.af_num(), $af_type);
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(Some(pin.map_into()), input_sel)
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}};
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}
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macro_rules! impl_spdifrx_pin {
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($inst:ident, $pin:ident, $af:expr, $sel:expr) => {
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impl crate::spdifrx::InPin<peripherals::$inst> for crate::peripherals::$pin {
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fn af_num(&self) -> u8 {
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$af
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}
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fn input_sel(&self) -> u8 {
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$sel
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}
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}
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};
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}
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/// Ring-buffered SPDIFRX driver.
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///
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/// Data is read by DMAs and stored in a ring buffer.
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#[cfg(not(gpdma))]
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pub struct Spdifrx<'d, T: Instance> {
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_peri: PeripheralRef<'d, T>,
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spdifrx_in: Option<PeripheralRef<'d, AnyPin>>,
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data_ring_buffer: ReadableRingBuffer<'d, u32>,
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}
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/// Gives the address of the data register.
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fn dr_address(r: Regs) -> *mut u32 {
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#[cfg(spdifrx_v1)]
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let address = r.dr().as_ptr() as _;
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#[cfg(spdifrx_h7)]
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let address = r.fmt0_dr().as_ptr() as _; // All fmtx_dr() implementations have the same address.
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return address;
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}
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/// Gives the address of the channel status register.
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#[allow(unused)]
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fn csr_address(r: Regs) -> *mut u32 {
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r.csr().as_ptr() as _
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}
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/// Select the channel for capturing control information.
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pub enum ControlChannelSelection {
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/// Capture control info from channel A.
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A,
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/// Capture control info from channel B.
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B,
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}
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/// Configuration options for the SPDIFRX driver.
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pub struct Config {
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/// Select the channel for capturing control information.
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pub control_channel_selection: ControlChannelSelection,
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}
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/// S/PDIF errors.
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#[derive(Debug)]
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pub enum Error {
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/// DMA overrun error.
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RingbufferError(RingbufferError),
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/// Left/right channel synchronization error.
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ChannelSyncError,
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}
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impl From<RingbufferError> for Error {
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fn from(error: RingbufferError) -> Self {
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Self::RingbufferError(error)
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}
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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control_channel_selection: ControlChannelSelection::A,
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}
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}
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}
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#[cfg(not(gpdma))]
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impl<'d, T: Instance> Spdifrx<'d, T> {
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fn dma_opts() -> TransferOptions {
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TransferOptions {
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half_transfer_ir: true,
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// new_write() and new_read() always use circular mode
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..Default::default()
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}
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}
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/// Create a new `Spdifrx` instance.
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::GlobalInterrupt, GlobalInterruptHandler<T>> + 'd,
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config: Config,
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spdifrx_in: impl Peripheral<P = impl InPin<T>> + 'd,
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data_dma: impl Peripheral<P = impl Channel + Dma<T>> + 'd,
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data_dma_buf: &'d mut [u32],
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) -> Self {
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let (spdifrx_in, input_sel) = new_spdifrx_pin!(spdifrx_in, AfType::input(Pull::None));
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Self::setup(config, input_sel);
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into_ref!(peri, data_dma);
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let regs = T::info().regs;
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let dr_request = data_dma.request();
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let dr_ring_buffer =
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unsafe { ReadableRingBuffer::new(data_dma, dr_request, dr_address(regs), data_dma_buf, Self::dma_opts()) };
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Self {
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_peri: peri,
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spdifrx_in,
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data_ring_buffer: dr_ring_buffer,
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}
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}
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fn setup(config: Config, input_sel: u8) {
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T::info().rcc.enable_and_reset();
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T::GlobalInterrupt::unpend();
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unsafe { T::GlobalInterrupt::enable() };
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let regs = T::info().regs;
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regs.imr().write(|imr| {
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imr.set_ifeie(true); // Enables interrupts for TERR, SERR, FERR.
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imr.set_syncdie(true); // Enables SYNCD interrupt.
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});
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regs.cr().write(|cr| {
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cr.set_spdifen(0x00); // Disable SPDIF receiver synchronization.
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cr.set_rxdmaen(true); // Use RX DMA for data. Enabled on `read`.
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cr.set_cbdmaen(false); // Do not capture channel info.
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cr.set_rxsteo(true); // Operate in stereo mode.
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cr.set_drfmt(0x01); // Data is left-aligned (MSB).
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// Disable all status fields in the data register.
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// Status can be obtained directly with the status register DMA.
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cr.set_pmsk(false); // Write parity bit to the data register. FIXME: Add parity check.
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cr.set_vmsk(false); // Write validity to the data register.
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cr.set_cumsk(true); // Do not write C and U bits to the data register.
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cr.set_ptmsk(false); // Write preamble bits to the data register.
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cr.set_chsel(match config.control_channel_selection {
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ControlChannelSelection::A => false,
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ControlChannelSelection::B => true,
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}); // Select channel status source.
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cr.set_nbtr(0x02); // 16 attempts are allowed.
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cr.set_wfa(true); // Wait for activity before going to synchronization phase.
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cr.set_insel(input_sel); // Input pin selection.
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#[cfg(stm32h7)]
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cr.set_cksen(true); // Generate a symbol clock.
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#[cfg(stm32h7)]
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cr.set_cksbkpen(true); // Generate a backup symbol clock.
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});
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}
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/// Start the SPDIFRX driver.
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pub fn start(&mut self) {
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self.data_ring_buffer.start();
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T::info().regs.cr().modify(|cr| {
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cr.set_spdifen(0x03); // Enable S/PDIF receiver.
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});
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}
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/// Read from the SPDIFRX data ring buffer.
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///
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/// SPDIFRX is always receiving data in the background. This function pops already-received
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/// data from the buffer.
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///
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/// If there's less than `data.len()` data in the buffer, this waits until there is.
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pub async fn read(&mut self, data: &mut [u32]) -> Result<(), Error> {
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self.data_ring_buffer.read_exact(data).await?;
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let first_preamble = (data[0] >> 4) & 0b11_u32;
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if (first_preamble as u8) == (PreambleType::W as u8) {
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trace!("S/PDIF left/right mismatch");
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// Resynchronize until the first sample is for the left channel.
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self.data_ring_buffer.clear();
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return Err(Error::ChannelSyncError);
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};
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for sample in data.as_mut() {
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if (*sample & (0x0002_u32)) == 0x0001 {
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// Discard invalid samples, setting them to mute level.
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*sample = 0;
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} else {
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// Discard status information in the lowest byte.
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*sample &= 0xFFFFFF00;
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}
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}
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Ok(())
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}
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}
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#[cfg(not(gpdma))]
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impl<'d, T: Instance> Drop for Spdifrx<'d, T> {
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fn drop(&mut self) {
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T::info().regs.cr().modify(|cr| cr.set_spdifen(0x00));
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self.spdifrx_in.as_ref().map(|x| x.set_as_disconnected());
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}
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}
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struct State {
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#[allow(unused)]
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waker: AtomicWaker,
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}
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impl State {
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const fn new() -> Self {
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Self {
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waker: AtomicWaker::new(),
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}
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}
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}
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struct Info {
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regs: crate::pac::spdifrx::Spdifrx,
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rcc: RccInfo,
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}
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peri_trait!(
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irqs: [GlobalInterrupt],
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);
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/// SPIDFRX pin trait
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pub trait InPin<T: Instance>: crate::gpio::Pin {
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/// Get the GPIO AF number needed to use this pin.
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fn af_num(&self) -> u8;
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/// Get the SPIDFRX INSEL number needed to use this pin.
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fn input_sel(&self) -> u8;
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}
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dma_trait!(Dma, Instance);
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/// Global interrupt handler.
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pub struct GlobalInterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::GlobalInterrupt> for GlobalInterruptHandler<T> {
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unsafe fn on_interrupt() {
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T::state().waker.wake();
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let regs = T::info().regs;
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let sr = regs.sr().read();
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if sr.serr() || sr.terr() || sr.ferr() {
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trace!("SPDIFRX error, resync");
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// Clear errors by disabling SPDIFRX, then reenable.
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regs.cr().modify(|cr| cr.set_spdifen(0x00));
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regs.cr().modify(|cr| cr.set_spdifen(0x03));
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} else if sr.syncd() {
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// Synchronization was successful.
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trace!("SPDIFRX sync success");
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}
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// Clear interrupt flags.
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regs.ifcr().write(|ifcr| {
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ifcr.set_perrcf(true); // Clears parity error flag.
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ifcr.set_ovrcf(true); // Clears overrun error flag.
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ifcr.set_sbdcf(true); // Clears synchronization block detected flag.
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ifcr.set_syncdcf(true); // Clears SYNCD from SR (was read above).
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});
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}
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}
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foreach_peripheral!(
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(spdifrx, $inst:ident) => {
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#[allow(private_interfaces)]
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impl SealedInstance for peripherals::$inst {
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fn info() -> &'static Info {
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static INFO: Info = Info{
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regs: crate::pac::$inst,
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rcc: crate::peripherals::$inst::RCC_INFO,
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};
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&INFO
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}
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fn state() -> &'static State {
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static STATE: State = State::new();
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&STATE
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}
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}
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impl Instance for peripherals::$inst {
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type GlobalInterrupt = crate::_generated::peripheral_interrupts::$inst::GLOBAL;
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}
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};
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);
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8
examples/stm32h723/.cargo/config.toml
Normal file
8
examples/stm32h723/.cargo/config.toml
Normal file
@ -0,0 +1,8 @@
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[target.thumbv7em-none-eabihf]
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runner = 'probe-rs run --chip STM32H723ZGTx'
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[build]
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target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
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[env]
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DEFMT_LOG = "trace"
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69
examples/stm32h723/Cargo.toml
Normal file
69
examples/stm32h723/Cargo.toml
Normal file
@ -0,0 +1,69 @@
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[package]
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edition = "2021"
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name = "embassy-stm32h7-examples"
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version = "0.1.0"
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license = "MIT OR Apache-2.0"
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[dependencies]
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# Change stm32h723zg to your chip name, if necessary.
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embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32h723zg", "time-driver-tim2", "exti", "memory-x", "unstable-pac", "chrono"] }
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embassy-sync = { version = "0.6.0", path = "../../embassy-sync", features = ["defmt"] }
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embassy-executor = { version = "0.6.2", path = "../../embassy-executor", features = ["task-arena-size-32768", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
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embassy-time = { version = "0.3.2", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
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embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
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defmt = "0.3"
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defmt-rtt = "0.4"
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cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
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cortex-m-rt = "0.7.0"
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embedded-hal = "0.2.6"
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embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
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embedded-hal-async = { version = "1.0" }
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embedded-nal-async = "0.8.0"
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embedded-io-async = { version = "0.6.1" }
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panic-probe = { version = "0.3", features = ["print-defmt"] }
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heapless = { version = "0.8", default-features = false }
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rand_core = "0.6.3"
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critical-section = "1.1"
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static_cell = "2"
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chrono = { version = "^0.4", default-features = false }
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grounded = "0.2.0"
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# cargo build/run
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[profile.dev]
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codegen-units = 1
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debug = 2
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debug-assertions = true # <-
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incremental = false
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opt-level = 3 # <-
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overflow-checks = true # <-
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# cargo test
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[profile.test]
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codegen-units = 1
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debug = 2
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debug-assertions = true # <-
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incremental = false
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opt-level = 3 # <-
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overflow-checks = true # <-
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# cargo build/run --release
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[profile.release]
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codegen-units = 1
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debug = 2
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debug-assertions = false # <-
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incremental = false
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lto = 'fat'
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opt-level = 3 # <-
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overflow-checks = false # <-
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# cargo test --release
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[profile.bench]
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codegen-units = 1
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debug = 2
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debug-assertions = false # <-
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incremental = false
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lto = 'fat'
|
||||
opt-level = 3 # <-
|
||||
overflow-checks = false # <-
|
||||
35
examples/stm32h723/build.rs
Normal file
35
examples/stm32h723/build.rs
Normal file
@ -0,0 +1,35 @@
|
||||
//! This build script copies the `memory.x` file from the crate root into
|
||||
//! a directory where the linker can always find it at build time.
|
||||
//! For many projects this is optional, as the linker always searches the
|
||||
//! project root directory -- wherever `Cargo.toml` is. However, if you
|
||||
//! are using a workspace or have a more complicated build setup, this
|
||||
//! build script becomes required. Additionally, by requesting that
|
||||
//! Cargo re-run the build script whenever `memory.x` is changed,
|
||||
//! updating `memory.x` ensures a rebuild of the application with the
|
||||
//! new memory settings.
|
||||
|
||||
use std::env;
|
||||
use std::fs::File;
|
||||
use std::io::Write;
|
||||
use std::path::PathBuf;
|
||||
|
||||
fn main() {
|
||||
// Put `memory.x` in our output directory and ensure it's
|
||||
// on the linker search path.
|
||||
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
|
||||
File::create(out.join("memory.x"))
|
||||
.unwrap()
|
||||
.write_all(include_bytes!("memory.x"))
|
||||
.unwrap();
|
||||
println!("cargo:rustc-link-search={}", out.display());
|
||||
|
||||
// By default, Cargo will re-run a build script whenever
|
||||
// any file in the project changes. By specifying `memory.x`
|
||||
// here, we ensure the build script is only re-run when
|
||||
// `memory.x` is changed.
|
||||
println!("cargo:rerun-if-changed=memory.x");
|
||||
|
||||
println!("cargo:rustc-link-arg-bins=--nmagic");
|
||||
println!("cargo:rustc-link-arg-bins=-Tlink.x");
|
||||
println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
|
||||
}
|
||||
106
examples/stm32h723/memory.x
Normal file
106
examples/stm32h723/memory.x
Normal file
@ -0,0 +1,106 @@
|
||||
MEMORY
|
||||
{
|
||||
/* This file is intended for parts in the STM32H723 family. (RM0468) */
|
||||
/* - FLASH and RAM are mandatory memory sections. */
|
||||
/* - The sum of all non-FLASH sections must add to 564k total device RAM. */
|
||||
/* - The FLASH section size must match your device, see table below. */
|
||||
|
||||
/* FLASH */
|
||||
/* Select the appropriate FLASH size for your device. */
|
||||
/* - STM32H730xB 128K */
|
||||
/* - STM32H723xE/725xE 512K */
|
||||
/* - STM32H723xG/725xG/733xG/735xG 1M */
|
||||
FLASH1 : ORIGIN = 0x08000000, LENGTH = 1M
|
||||
|
||||
/* Data TCM */
|
||||
/* - Two contiguous 64KB RAMs. */
|
||||
/* - Used for interrupt handlers, stacks and general RAM. */
|
||||
/* - Zero wait-states. */
|
||||
/* - The DTCM is taken as the origin of the base ram. (See below.) */
|
||||
/* This is also where the interrupt table and such will live, */
|
||||
/* which is required for deterministic performance. */
|
||||
DTCM : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
|
||||
/* Instruction TCM */
|
||||
/* - More memory can be assigned to ITCM. See AXI SRAM notes, below. */
|
||||
/* - Used for latency-critical interrupt handlers etc. */
|
||||
/* - Zero wait-states. */
|
||||
ITCM : ORIGIN = 0x00000000, LENGTH = 64K + 0K
|
||||
|
||||
/* AXI SRAM */
|
||||
/* - AXISRAM is in D1 and accessible by all system masters except BDMA. */
|
||||
/* - Suitable for application data not stored in DTCM. */
|
||||
/* - Zero wait-states. */
|
||||
/* - The 192k of extra shared RAM is fully allotted to the AXI SRAM by default. */
|
||||
/* As a result: 64k (64k + 0k) for ITCM and 320k (128k + 192k) for AXI SRAM. */
|
||||
/* This can be re-configured via the TCM_AXI_SHARED[1,0] register when more */
|
||||
/* ITCM is required. */
|
||||
AXISRAM : ORIGIN = 0x24000000, LENGTH = 128K + 192K
|
||||
|
||||
/* AHB SRAM */
|
||||
/* - SRAM1-2 are in D2 and accessible by all system masters except BDMA, LTDC */
|
||||
/* and SDMMC1. Suitable for use as DMA buffers. */
|
||||
/* - SRAM4 is in D3 and additionally accessible by the BDMA. Used for BDMA */
|
||||
/* buffers, for storing application data in lower-power modes. */
|
||||
/* - Zero wait-states. */
|
||||
SRAM1 : ORIGIN = 0x30000000, LENGTH = 16K
|
||||
SRAM2 : ORIGIN = 0x30040000, LENGTH = 16K
|
||||
SRAM4 : ORIGIN = 0x38000000, LENGTH = 16K
|
||||
|
||||
/* Backup SRAM */
|
||||
/* Used to store data during low-power sleeps. */
|
||||
BSRAM : ORIGIN = 0x38800000, LENGTH = 4K
|
||||
}
|
||||
|
||||
/*
|
||||
/* Assign the memory regions defined above for use. */
|
||||
/*
|
||||
|
||||
/* Provide the mandatory FLASH and RAM definitions for cortex-m-rt's linker script. */
|
||||
REGION_ALIAS(FLASH, FLASH1);
|
||||
REGION_ALIAS(RAM, DTCM);
|
||||
|
||||
/* The location of the stack can be overridden using the `_stack_start` symbol. */
|
||||
/* - Set the stack location at the end of RAM, using all remaining space. */
|
||||
_stack_start = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
/* The location of the .text section can be overridden using the */
|
||||
/* `_stext` symbol. By default it will place after .vector_table. */
|
||||
/* _stext = ORIGIN(FLASH) + 0x40c; */
|
||||
|
||||
/* Define sections for placing symbols into the extra memory regions above. */
|
||||
/* This makes them accessible from code. */
|
||||
/* - ITCM, DTCM and AXISRAM connect to a 64-bit wide bus -> align to 8 bytes. */
|
||||
/* - All other memories connect to a 32-bit wide bus -> align to 4 bytes. */
|
||||
SECTIONS {
|
||||
.itcm (NOLOAD) : ALIGN(8) {
|
||||
*(.itcm .itcm.*);
|
||||
. = ALIGN(8);
|
||||
} > ITCM
|
||||
|
||||
.axisram (NOLOAD) : ALIGN(8) {
|
||||
*(.axisram .axisram.*);
|
||||
. = ALIGN(8);
|
||||
} > AXISRAM
|
||||
|
||||
.sram1 (NOLOAD) : ALIGN(4) {
|
||||
*(.sram1 .sram1.*);
|
||||
. = ALIGN(4);
|
||||
} > SRAM1
|
||||
|
||||
.sram2 (NOLOAD) : ALIGN(4) {
|
||||
*(.sram2 .sram2.*);
|
||||
. = ALIGN(4);
|
||||
} > SRAM2
|
||||
|
||||
.sram4 (NOLOAD) : ALIGN(4) {
|
||||
*(.sram4 .sram4.*);
|
||||
. = ALIGN(4);
|
||||
} > SRAM4
|
||||
|
||||
.bsram (NOLOAD) : ALIGN(4) {
|
||||
*(.bsram .bsram.*);
|
||||
. = ALIGN(4);
|
||||
} > BSRAM
|
||||
|
||||
};
|
||||
165
examples/stm32h723/src/bin/spdifrx.rs
Normal file
165
examples/stm32h723/src/bin/spdifrx.rs
Normal file
@ -0,0 +1,165 @@
|
||||
//! This example receives inputs on SPDIFRX and outputs on SAI4.
|
||||
//!
|
||||
//! Only very few controllers connect the SPDIFRX symbol clock to a SAI peripheral's clock input.
|
||||
//! However, this is necessary for synchronizing the symbol rates and avoiding glitches.
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
use defmt::{info, trace};
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_futures::select::{self, select, Either};
|
||||
use embassy_stm32::spdifrx::{self, Spdifrx};
|
||||
use embassy_stm32::{bind_interrupts, peripherals, sai};
|
||||
use grounded::uninit::GroundedArrayCell;
|
||||
use hal::sai::*;
|
||||
use {defmt_rtt as _, embassy_stm32 as hal, panic_probe as _};
|
||||
|
||||
bind_interrupts!(struct Irqs {
|
||||
SPDIF_RX => spdifrx::GlobalInterruptHandler<peripherals::SPDIFRX1>;
|
||||
});
|
||||
|
||||
const CHANNEL_COUNT: usize = 2;
|
||||
const BLOCK_LENGTH: usize = 64;
|
||||
const HALF_DMA_BUFFER_LENGTH: usize = BLOCK_LENGTH * CHANNEL_COUNT;
|
||||
const DMA_BUFFER_LENGTH: usize = HALF_DMA_BUFFER_LENGTH * 2; // 2 half-blocks
|
||||
|
||||
// DMA buffers must be in special regions. Refer https://embassy.dev/book/#_stm32_bdma_only_working_out_of_some_ram_regions
|
||||
#[link_section = ".sram1"]
|
||||
static mut SPDIFRX_BUFFER: GroundedArrayCell<u32, DMA_BUFFER_LENGTH> = GroundedArrayCell::uninit();
|
||||
|
||||
#[link_section = ".sram4"]
|
||||
static mut SAI_BUFFER: GroundedArrayCell<u32, DMA_BUFFER_LENGTH> = GroundedArrayCell::uninit();
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let mut peripheral_config = embassy_stm32::Config::default();
|
||||
{
|
||||
use embassy_stm32::rcc::*;
|
||||
peripheral_config.rcc.hsi = Some(HSIPrescaler::DIV1);
|
||||
peripheral_config.rcc.pll1 = Some(Pll {
|
||||
source: PllSource::HSI,
|
||||
prediv: PllPreDiv::DIV16,
|
||||
mul: PllMul::MUL200,
|
||||
divp: Some(PllDiv::DIV2), // 400 MHz
|
||||
divq: Some(PllDiv::DIV2),
|
||||
divr: Some(PllDiv::DIV2),
|
||||
});
|
||||
peripheral_config.rcc.sys = Sysclk::PLL1_P;
|
||||
peripheral_config.rcc.ahb_pre = AHBPrescaler::DIV2;
|
||||
peripheral_config.rcc.apb1_pre = APBPrescaler::DIV2;
|
||||
peripheral_config.rcc.apb2_pre = APBPrescaler::DIV2;
|
||||
peripheral_config.rcc.apb3_pre = APBPrescaler::DIV2;
|
||||
peripheral_config.rcc.apb4_pre = APBPrescaler::DIV2;
|
||||
|
||||
peripheral_config.rcc.mux.spdifrxsel = mux::Spdifrxsel::PLL1_Q;
|
||||
}
|
||||
let mut p = embassy_stm32::init(peripheral_config);
|
||||
|
||||
info!("SPDIFRX to SAI4 bridge");
|
||||
|
||||
// Use SPDIFRX clock for SAI.
|
||||
// This ensures equal rates of sample production and consumption.
|
||||
let clk_source = embassy_stm32::pac::rcc::vals::Saiasel::_RESERVED_5;
|
||||
embassy_stm32::pac::RCC.d3ccipr().modify(|w| {
|
||||
w.set_sai4asel(clk_source);
|
||||
});
|
||||
|
||||
let sai_buffer: &mut [u32] = unsafe {
|
||||
SAI_BUFFER.initialize_all_copied(0);
|
||||
let (ptr, len) = SAI_BUFFER.get_ptr_len();
|
||||
core::slice::from_raw_parts_mut(ptr, len)
|
||||
};
|
||||
|
||||
let spdifrx_buffer: &mut [u32] = unsafe {
|
||||
SPDIFRX_BUFFER.initialize_all_copied(0);
|
||||
let (ptr, len) = SPDIFRX_BUFFER.get_ptr_len();
|
||||
core::slice::from_raw_parts_mut(ptr, len)
|
||||
};
|
||||
|
||||
let mut sai_transmitter = new_sai_transmitter(
|
||||
&mut p.SAI4,
|
||||
&mut p.PD13,
|
||||
&mut p.PC1,
|
||||
&mut p.PD12,
|
||||
&mut p.BDMA_CH0,
|
||||
sai_buffer,
|
||||
);
|
||||
let mut spdif_receiver = new_spdif_receiver(&mut p.SPDIFRX1, &mut p.PD7, &mut p.DMA2_CH7, spdifrx_buffer);
|
||||
spdif_receiver.start();
|
||||
|
||||
let mut renew_sai = false;
|
||||
loop {
|
||||
let mut buf = [0u32; HALF_DMA_BUFFER_LENGTH];
|
||||
|
||||
if renew_sai {
|
||||
renew_sai = false;
|
||||
trace!("Renew SAI.");
|
||||
drop(sai_transmitter);
|
||||
sai_transmitter = new_sai_transmitter(
|
||||
&mut p.SAI4,
|
||||
&mut p.PD13,
|
||||
&mut p.PC1,
|
||||
&mut p.PD12,
|
||||
&mut p.BDMA_CH0,
|
||||
sai_buffer,
|
||||
);
|
||||
}
|
||||
|
||||
match select(spdif_receiver.read(&mut buf), sai_transmitter.wait_write_error()).await {
|
||||
Either::First(spdif_read_result) => match spdif_read_result {
|
||||
Ok(_) => (),
|
||||
Err(spdifrx::Error::RingbufferError(_)) => {
|
||||
trace!("SPDIFRX ringbuffer error. Renew.");
|
||||
drop(spdif_receiver);
|
||||
spdif_receiver = new_spdif_receiver(&mut p.SPDIFRX1, &mut p.PD7, &mut p.DMA2_CH7, spdifrx_buffer);
|
||||
spdif_receiver.start();
|
||||
continue;
|
||||
}
|
||||
Err(spdifrx::Error::ChannelSyncError) => {
|
||||
trace!("SPDIFRX channel sync (left/right assignment) error.");
|
||||
continue;
|
||||
}
|
||||
},
|
||||
Either::Second(_) => {
|
||||
renew_sai = true;
|
||||
continue;
|
||||
}
|
||||
};
|
||||
|
||||
renew_sai = sai_transmitter.write(&buf).await.is_err();
|
||||
}
|
||||
}
|
||||
|
||||
/// Creates a new SPDIFRX instance for receiving sample data.
|
||||
///
|
||||
/// Used (again) after dropping the SPDIFRX instance, in case of errors (e.g. source disconnect).
|
||||
fn new_spdif_receiver<'d>(
|
||||
spdifrx: &'d mut peripherals::SPDIFRX1,
|
||||
input_pin: &'d mut peripherals::PD7,
|
||||
dma: &'d mut peripherals::DMA2_CH7,
|
||||
buf: &'d mut [u32],
|
||||
) -> Spdifrx<'d, peripherals::SPDIFRX1> {
|
||||
Spdifrx::new(spdifrx, Irqs, spdifrx::Config::default(), input_pin, dma, buf)
|
||||
}
|
||||
|
||||
/// Creates a new SAI4 instance for transmitting sample data.
|
||||
///
|
||||
/// Used (again) after dropping the SAI4 instance, in case of errors (e.g. buffer overrun).
|
||||
fn new_sai_transmitter<'d>(
|
||||
sai: &'d mut peripherals::SAI4,
|
||||
sck: &'d mut peripherals::PD13,
|
||||
sd: &'d mut peripherals::PC1,
|
||||
fs: &'d mut peripherals::PD12,
|
||||
dma: &'d mut peripherals::BDMA_CH0,
|
||||
buf: &'d mut [u32],
|
||||
) -> Sai<'d, peripherals::SAI4, u32> {
|
||||
let mut sai_config = hal::sai::Config::default();
|
||||
sai_config.slot_count = hal::sai::word::U4(CHANNEL_COUNT as u8);
|
||||
sai_config.slot_enable = 0xFFFF; // All slots
|
||||
sai_config.data_size = sai::DataSize::Data32;
|
||||
sai_config.frame_length = (CHANNEL_COUNT * 32) as u8;
|
||||
sai_config.master_clock_divider = hal::sai::MasterClockDivider::MasterClockDisabled;
|
||||
|
||||
let (sub_block_tx, _) = hal::sai::split_subblocks(sai);
|
||||
Sai::new_asynchronous(sub_block_tx, sck, sd, fs, dma, buf, sai_config)
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user