From 1ce9418bca64b0783f6837256bef451312922717 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Tue, 25 Jun 2024 23:55:07 +0200 Subject: [PATCH] nrf/buffered_uart: take into account EASYDMA_SIZE. fixes nrf52832 --- embassy-nrf/src/buffered_uarte.rs | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs index 071c18760..8e4064aaa 100644 --- a/embassy-nrf/src/buffered_uarte.rs +++ b/embassy-nrf/src/buffered_uarte.rs @@ -27,7 +27,7 @@ use crate::ppi::{ }; use crate::timer::{Instance as TimerInstance, Timer}; use crate::uarte::{configure, drop_tx_rx, Config, Instance as UarteInstance}; -use crate::{interrupt, pac, Peripheral}; +use crate::{interrupt, pac, Peripheral, EASY_DMA_SIZE}; pub(crate) struct State { tx_buf: RingBuffer, @@ -186,6 +186,7 @@ impl interrupt::typelevel::Handler for Interrupt // If not TXing, start. if s.tx_count.load(Ordering::Relaxed) == 0 { let (ptr, len) = tx.pop_buf(); + let len = len.min(EASY_DMA_SIZE); if len != 0 { //trace!(" irq_tx: starting {:?}", len); s.tx_count.store(len, Ordering::Relaxed); @@ -641,8 +642,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> { s.rx_started_count.store(0, Ordering::Relaxed); s.rx_ended_count.store(0, Ordering::Relaxed); s.rx_started.store(false, Ordering::Relaxed); - let len = rx_buffer.len(); - unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), len) }; + let rx_len = rx_buffer.len().min(EASY_DMA_SIZE * 2); + unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), rx_len) }; // clear errors let errors = r.errorsrc.read().bits(); @@ -663,7 +664,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> { // Configure byte counter. let timer = Timer::new_counter(timer); - timer.cc(1).write(rx_buffer.len() as u32 * 2); + timer.cc(1).write(rx_len as u32 * 2); timer.cc(1).short_compare_clear(); timer.clear(); timer.start();