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stm32/adc: add h7rs support.

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This commit is contained in:
Dario Nieuwenhuis 2025-04-25 00:09:13 +02:00
parent b32ff0c8f7
commit 18eea73d19
2 changed files with 13 additions and 11 deletions
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4
embassy-stm32/src/adc/mod.rs
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@ -11,7 +11,7 @@
#[cfg_attr(adc_v1, path = "v1.rs")]
#[cfg_attr(adc_l0, path = "v1.rs")]
#[cfg_attr(adc_v2, path = "v2.rs")]
#[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_u0), path = "v3.rs")]
#[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0), path = "v3.rs")]
#[cfg_attr(any(adc_v4, adc_u5), path = "v4.rs")]
#[cfg_attr(adc_g4, path = "g4.rs")]
#[cfg_attr(adc_c0, path = "c0.rs")]
@ -108,6 +108,7 @@ pub(crate) fn blocking_delay_us(us: u32) {
adc_g0,
adc_u0,
adc_h5,
adc_h7rs,
adc_u5,
adc_c0
)))]
@ -129,6 +130,7 @@ pub trait Instance: SealedInstance + crate::PeripheralType {
adc_g0,
adc_u0,
adc_h5,
adc_h7rs,
adc_u5,
adc_c0
))]

20
embassy-stm32/src/adc/v3.rs
View File

@ -19,7 +19,7 @@ impl<T: Instance> SealedAdcChannel<T> for VrefInt {
cfg_if! {
if #[cfg(adc_g0)] {
let val = 13;
} else if #[cfg(adc_h5)] {
} else if #[cfg(any(adc_h5, adc_h7rs))] {
let val = 17;
} else if #[cfg(adc_u0)] {
let val = 12;
@ -38,7 +38,7 @@ impl<T: Instance> SealedAdcChannel<T> for Temperature {
cfg_if! {
if #[cfg(adc_g0)] {
let val = 12;
} else if #[cfg(adc_h5)] {
} else if #[cfg(any(adc_h5, adc_h7rs))] {
let val = 16;
} else if #[cfg(adc_u0)] {
let val = 11;
@ -57,9 +57,9 @@ impl<T: Instance> SealedAdcChannel<T> for Vbat {
cfg_if! {
if #[cfg(adc_g0)] {
let val = 14;
} else if #[cfg(adc_h5)] {
} else if #[cfg(any(adc_h5, adc_h7rs))] {
let val = 2;
} else if #[cfg(adc_h5)] {
} else if #[cfg(any(adc_h5, adc_h7rs))] {
let val = 13;
} else {
let val = 18;
@ -70,7 +70,7 @@ impl<T: Instance> SealedAdcChannel<T> for Vbat {
}
cfg_if! {
if #[cfg(adc_h5)] {
if #[cfg(any(adc_h5, adc_h7rs))] {
pub struct VddCore;
impl<T: Instance> AdcChannel<T> for VddCore {}
impl<T: Instance> super::SealedAdcChannel<T> for VddCore {
@ -171,7 +171,7 @@ impl<'d, T: Instance> Adc<'d, T> {
T::regs().ccr().modify(|reg| {
reg.set_tsen(true);
});
} else if #[cfg(adc_h5)] {
} else if #[cfg(any(adc_h5, adc_h7rs))] {
T::common_regs().ccr().modify(|reg| {
reg.set_tsen(true);
});
@ -191,7 +191,7 @@ impl<'d, T: Instance> Adc<'d, T> {
T::regs().ccr().modify(|reg| {
reg.set_vbaten(true);
});
} else if #[cfg(adc_h5)] {
} else if #[cfg(any(adc_h5, adc_h7rs))] {
T::common_regs().ccr().modify(|reg| {
reg.set_vbaten(true);
});
@ -414,7 +414,7 @@ impl<'d, T: Instance> Adc<'d, T> {
fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
// RM0492, RM0481, etc.
// "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
#[cfg(adc_h5)]
#[cfg(any(adc_h5, adc_h7rs))]
if channel.channel() == 0 {
T::regs().or().modify(|reg| reg.set_op0(true));
}
@ -447,7 +447,7 @@ impl<'d, T: Instance> Adc<'d, T> {
// RM0492, RM0481, etc.
// "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
#[cfg(adc_h5)]
#[cfg(any(adc_h5, adc_h7rs))]
if channel.channel() == 0 {
T::regs().or().modify(|reg| reg.set_op0(false));
}
@ -475,7 +475,7 @@ impl<'d, T: Instance> Adc<'d, T> {
if #[cfg(any(adc_g0, adc_u0))] {
// On G0 and U6 all channels use the same sampling time.
T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
} else if #[cfg(adc_h5)] {
} else if #[cfg(any(adc_h5, adc_h7rs))] {
match _ch {
0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
_ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),