commit
17cce79807
@ -887,6 +887,16 @@ impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
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})
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.await;
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// Errata for STM32H5, 2.20.1:
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// During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses
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// have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct.
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//
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// Workaround:
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// Software should ensure that a small delay is included before accessing the SRAM contents. This delay should be
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// 800 ns in Full Speed mode and 6.4 μs in Low Speed mode.
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#[cfg(stm32h5)]
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embassy_time::block_for(embassy_time::Duration::from_nanos(800));
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RX_COMPLETE[index].store(false, Ordering::Relaxed);
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if stat == Stat::DISABLED {
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@ -348,7 +348,7 @@ pub struct AudioSettings {
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impl Default for AudioSettings {
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fn default() -> Self {
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AudioSettings {
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muted: [true; MAX_AUDIO_CHANNEL_COUNT],
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muted: [false; MAX_AUDIO_CHANNEL_COUNT],
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volume_8q8_db: [MAX_VOLUME_DB * VOLUME_STEPS_PER_DB; MAX_AUDIO_CHANNEL_COUNT],
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}
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}
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