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fix: apply STM32H5 USB errata (OUT transfer delay)

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elagil 2025-03-22 11:46:28 +01:00
parent 4033a619a8
commit 07387ea405
1 changed files with 11 additions and 0 deletions
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11
embassy-stm32/src/usb/usb.rs
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@ -7,6 +7,7 @@ use core::task::Poll;
use embassy_hal_internal::into_ref; use embassy_hal_internal::into_ref;
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
use embassy_time::Timer;
use embassy_usb_driver as driver; use embassy_usb_driver as driver;
use embassy_usb_driver::{ use embassy_usb_driver::{
Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported, Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported,
@ -887,6 +888,16 @@ impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
}) })
.await; .await;
// Errata for STM32H5, 2.20.1:
// During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses
// have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct.
//
// Workaround:
// Software should ensure that a small delay is included before accessing the SRAM contents. This delay should be
// 800 ns in Full Speed mode and 6.4 μs in Low Speed mode.
#[cfg(stm32h5)]
Timer::after_nanos(800).await;
RX_COMPLETE[index].store(false, Ordering::Relaxed); RX_COMPLETE[index].store(false, Ordering::Relaxed);
if stat == Stat::DISABLED { if stat == Stat::DISABLED {