A small can/usb adapter for running candlelight firmware

This commit is contained in:
Pontus Borg
2022-02-09 15:11:45 +01:00
parent 062164cb68
commit fa9ed991d3
8 changed files with 12014 additions and 0 deletions

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update=30/01/2021 09:01:09
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.3
TrackWidth3=0.4
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 2
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 2050 4100 2050 1550
U 6014FB17
F0 "Sheet6014FB16" 50
F1 "file6014FB16.sch" 50
$EndSheet
$EndSCHEMATC

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#(c) SnapEDA 2016 (snapeda.com)
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
#
# 48037-0001
#
DEF 48037-0001 J 0 40 Y Y 1 L N
F0 "J" -200 350 50 H V L BNN
F1 "48037-0001" -200 -500 50 H V L BNN
F2 "MOLEX_48037-0001" 0 0 50 H I L BNN
F3 "" 0 0 50 H I L BNN
F4 "Manufacturer Recommendations" 0 0 50 H I L BNN "STANDARD"
F5 "Molex" 0 0 50 H I L BNN "MANUFACTURER"
F6 "D" 0 0 50 H I L BNN "PARTREV"
F7 "4.6mm" 0 0 50 H I L BNN "MAXIMUM_PACKAGE_HEIGHT"
DRAW
S -200 -400 200 300 0 0 10 f
X VCC 1 -400 200 200 R 40 40 0 0 W
X D- 2 -400 100 200 R 40 40 0 0 B
X D+ 3 -400 0 200 R 40 40 0 0 B
X GND 4 -400 -100 200 R 40 40 0 0 W
X SHIELD S1 -400 -300 200 R 40 40 0 0 P
X SHIELD S2 -400 -300 200 R 40 40 0 0 P
ENDDRAW
ENDDEF
#
# End Library

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(module MOLEX_48037-0001 (layer F.Cu) (tedit 6023D709)
(descr "")
(fp_text reference REF** (at -3.725 -4.235 0) (layer F.SilkS)
(effects (font (size 1.0 1.0) (thickness 0.015)))
)
(fp_text value MOLEX_48037-0001 (at 3.26 18.965 0) (layer F.Fab)
(effects (font (size 1.0 1.0) (thickness 0.015)))
)
(fp_line (start -6.0 -1.0) (end -6.0 2.75) (layer F.Fab) (width 0.127))
(fp_line (start -6.0 2.75) (end 6.0 2.75) (layer F.Fab) (width 0.127))
(fp_line (start 6.0 2.75) (end 6.0 -1.0) (layer F.Fab) (width 0.127))
(fp_line (start 6.0 -1.0) (end -6.0 -1.0) (layer F.Fab) (width 0.127))
(fp_line (start -6.0 2.75) (end -6.0 17.8) (layer F.Fab) (width 0.127))
(fp_line (start -6.0 17.8) (end 6.0 17.8) (layer F.Fab) (width 0.127))
(fp_text user PCB~EDGE (at 6.28 2.47) (layer F.Fab)
(effects (font (size 0.32 0.32) (thickness 0.015)))
)
(fp_line (start 6.0 17.8) (end 6.0 2.75) (layer F.Fab) (width 0.127))
(fp_line (start 6.0 2.75) (end 9.2 2.75) (layer F.Fab) (width 0.127))
(fp_line (start -6.0 2.0) (end -6.0 2.75) (layer F.SilkS) (width 0.127))
(fp_line (start -6.0 2.75) (end 6.0 2.75) (layer F.SilkS) (width 0.127))
(fp_line (start 6.0 2.75) (end 6.0 2.0) (layer F.SilkS) (width 0.127))
(fp_line (start -6.75 -3.11) (end -6.75 18.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.75 18.05) (end 6.75 18.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.75 18.05) (end 6.75 -3.11) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.75 -3.11) (end -6.75 -3.11) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.0 2.75) (end -6.0 17.8) (layer F.SilkS) (width 0.127))
(fp_line (start -6.0 17.8) (end 6.0 17.8) (layer F.SilkS) (width 0.127))
(fp_line (start 6.0 17.8) (end 6.0 2.75) (layer F.SilkS) (width 0.127))
(fp_circle (center 3.5 -3.4) (end 3.6 -3.4) (layer F.SilkS) (width 0.2))
(fp_circle (center 3.5 -3.4) (end 3.6 -3.4) (layer F.Fab) (width 0.2))
(pad 1 thru_hole rect (at 3.5 -2.1) (size 1.508 1.508) (drill 1.0) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at 1.0 -2.1) (size 1.508 1.508) (drill 1.0) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at -1.0 -2.1) (size 1.508 1.508) (drill 1.0) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at -3.5 -2.1) (size 1.508 1.508) (drill 1.0) (layers *.Cu *.Mask))
(pad None np_thru_hole circle (at 2.25 0.0) (size 1.25 1.25) (drill 1.25) (layers *.Cu *.Mask))
(pad None np_thru_hole circle (at -2.25 0.0) (size 1.25 1.25) (drill 1.25) (layers *.Cu *.Mask))
(pad S2 thru_hole oval (at -5.7 0.0) (size 1.575 3.15) (drill oval 1.05 2.6) (layers *.Cu *.Mask))
(pad S1 thru_hole oval (at 5.7 0.0) (size 1.575 3.15) (drill oval 1.05 2.6) (layers *.Cu *.Mask))
)

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