HR/PEE20_motionController
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add frequency option

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This commit is contained in:
Mats van Reenen 2020-05-22 17:12:31 +02:00
parent 977c26b2ca
commit 2d38b034ac
4 changed files with 240 additions and 214 deletions
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155
SPI.c
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@ -1,65 +1,90 @@
#include <msp430.h> #include <msp430.h>
#include "SPI.h" #include "SPI.h"
uchar SPI_CS; uchar SPI_CS = 0;
int SPIInit(){ int SPIInit(){
UCA0CTL1 = UCSWRST; UCA0CTL1 = UCSWRST;
// setup A0 for SPI // setup A0 for SPI
UCA0CTL0 = SPI_Mode3 | UCMSB | UCMST | (0x10 << 1) | UCSYNC; UCA0CTL0 = UCMSB | UCMST | (0x10 << 1) | UCSYNC;
UCA0CTL1 |= UCSSEL_2; UCA0CTL1 |= UCSSEL_2;
UCA0BR1 = 0; //TODO: set corect frequency UCA0BR1 = 0;
UCA0BR0 = 4; UCA0BR0 = 16; // 1 MHz
// config port // config port
//set SEL to USCI (0b01); MOSI (pin 1), MISO (pin 2), CLK (pin 4) //set SEL to USCI (0b01); MOSI (pin 1), MISO (pin 2), CLK (pin 4)
P1SEL |= BIT1 | BIT2 | BIT4; P1SEL |= BIT1 | BIT2 | BIT4;
P1SEL2 |= BIT1 | BIT2 | BIT4; P1SEL2 |= BIT1 | BIT2 | BIT4;
UCA0CTL1 &= ~UCSWRST; UCA0CTL1 &= ~UCSWRST;
// enable interrupts // enable interrupts
IE2 |= UCA0TXIE; // IE2 |= UCA0TXIE;
IFG2 &= ~UCA0TXIFG; // IFG2 &= ~UCA0TXIFG;
// set initial values for vars // set initial values for vars
SPI_packetC = 0; SPI_packetC = 0;
SPI_CS = 0; SPI_CS = 0;
__enable_interrupt(); __enable_interrupt();
return 0; return 0;
} }
void SPISend(){ //TODO: add clock freqency configuration
P1OUT &= ~SPI_CS; /*
UCA0TXBUF = SPI_packet[SPI_packetC]; * do some configuration before sending the data.
} *
* @arg uchar cs: the bit of port 1 connected to the chip select pin of target device
void SPIInitSend(uchar cs, enum SPI_Mode mode){ * @arg enum SPI_Mode: the SPI modus (clock pase and polarity)
while(SPI_CS != 0) * @arg enum SPI_clock: the clock freqency
//TODO: search for a more power effient way for a delay */
__delay_cycles (16000); void SPIInitSend(uchar cs, enum SPI_Mode mode, enum SPI_Clock clk){
//TODO: add a clock as powerefficent delay
UCA0CTL0 |= mode; while(SPI_CS != 0); // wait for last transmit to be done
UCA0CTL0 &= ~mode ^ 0xC0;
SPI_CS = cs; // set clock frequency
} UCA0BR0 = clk;
#pragma vector = USCIAB0TX_VECTOR // set SPI mode
__interrupt void ISR_EUSCI_A0(){ UCA0CTL0 &= 0x3F; // set mode bits to 0
SPI_packet[SPI_packetC] = UCA0RXIFG; UCA0CTL0 |= mode;
if(SPI_packetC == 4){
P1OUT |= SPI_CS; // save chip select
SPI_packetC = 0; SPI_CS = cs;
IFG2 &= ~UCA0TXIFG; }
SPI_CS = 0;
}else{ //TODO: make it asyncronily with interupt.
SPI_packetC++; /*
UCA0TXBUF = SPI_packet[SPI_packetC]; * Send the packet stored in SPI_packet. it start from SPI_packetC to the last byte
} */
} void SPISend(){
P1OUT &= ~SPI_CS; // select slave
while(SPI_packetC < 5){
// send one byte
UCA0TXBUF = SPI_packet[SPI_packetC];
//TODO: fix the delay! it's to short with low data speeds
if(UCA0BR0 > 4)
// if de frequency lower than 4 MHz do a manual delay. this is a workaround for the to short delay
// this works down to 1 MHz
__delay_cycles(129);
else
while(UCB0STAT & UCBUSY); // wait for SPI TX/RX to finish
// save recieved data
SPI_packet[SPI_packetC] = UCA0RXIFG;
// increase counter for next byte
SPI_packetC++;
}
SPI_packetC = 0; // recet counter
P1OUT |= SPI_CS; // deselect slave
SPI_CS = 0;
}

45
SPI.h
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@ -1,22 +1,23 @@
/* /*
* SPI.c * SPI.c
* *
* Created on: 4 mei 2020 * Created on: 4 mei 2020
* Author: mreenen * Author: mreenen
*/ */
#ifndef SPI_C_ #ifndef SPI_C_
#define SPI_C_ #define SPI_C_
#include "typedefExtention.h" #include "typedefExtention.h"
enum SPI_Mode {SPI_Mode0=0b00<<6, SPI_Mode1=0b10<<6, SPI_Mode2=0b11<<6, SPI_Mode3=0b01<<6}; enum SPI_Mode {SPI_Mode0=0b00<<6, SPI_Mode1=0b10<<6, SPI_Mode2=0b11<<6, SPI_Mode3=0b01<<6};
enum SPI_Clock {SPI_Clock_1MHz=16, SPI_Clock_2MHz=8, SPI_Clock_4MHz=4, SPI_Clock_8MHz=2};
uchar SPI_packet[5];
char SPI_packetC; uchar SPI_packet[5];
char SPI_packetC;
int SPIInit();
void SPISend(); int SPIInit();
void SPIInitSend(uchar cs, enum SPI_Mode mode); void SPISend();
void SPIInitSend(uchar cs, enum SPI_Mode mode, enum SPI_Clock clk);
#endif /* SPI_C_ */
#endif /* SPI_C_ */

6
motionController.c
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@ -88,7 +88,7 @@ void MC_write(uchar addr, ulong data) {
char i; char i;
// wait for SPI bus to be available // wait for SPI bus to be available
SPIInitSend(MC_CS, SPI_Mode3); SPIInitSend(MC_CS, SPI_Mode3, SPI_Clock_1MHz);
// set write bit to write // set write bit to write
addr &= ~0x01; addr &= ~0x01;
@ -109,7 +109,7 @@ ulong MC_read(unsigned char addr) {
ulong data; ulong data;
// wait for SPI bus to be available // wait for SPI bus to be available
SPIInitSend(MC_CS, SPI_Mode3); SPIInitSend(MC_CS, SPI_Mode3, SPI_Clock_1MHz);
// set write bit to read // set write bit to read
addr |= 0x01; addr |= 0x01;
@ -119,7 +119,7 @@ ulong MC_read(unsigned char addr) {
SPISend(); SPISend();
// wait for SPI bus to be available // wait for SPI bus to be available
SPIInitSend(MC_CS, SPI_Mode3); SPIInitSend(MC_CS, SPI_Mode3, SPI_Clock_1MHz);
// set write bit to read // set write bit to read
addr |= 0x01; addr |= 0x01;

248
motorDriver.c
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@ -1,124 +1,124 @@
/* /*
* motorDriver.c * motorDriver.c
* *
* Created on: 4 mei 2020 * Created on: 4 mei 2020
* Author: mreenen * Author: mreenen
*/ */
#include <msp430.h> #include <msp430.h>
#include "typedefExtention.h" #include "typedefExtention.h"
#include "SPI.h" #include "SPI.h"
#include "motorDriver.h" #include "motorDriver.h"
const uchar MD_CS = BIT3; const uchar MD_CS = BIT3;
// register 0x00 GCINF // register 0x00 GCINF
#define MD_GCONF 0X00 #define MD_GCONF 0X00
#define MD_GCONF_singgelMotor 0x00000001 #define MD_GCONF_singgelMotor 0x00000001
#define MD_GCONF_stepdir1Enable 0x00000002 #define MD_GCONF_stepdir1Enable 0x00000002
#define MD_GCONF_stepdir2Enable 0x00000004 #define MD_GCONF_stepdir2Enable 0x00000004
#define MD_GCONF_motor1Revers 0x00000010 #define MD_GCONF_motor1Revers 0x00000010
#define MD_GCONF_motor1Revers 0x00000010 #define MD_GCONF_motor1Revers 0x00000010
#define MD_GCONF_lockGCONF 0x00000020 #define MD_GCONF_lockGCONF 0x00000020
// register 0x01 GSTAT // register 0x01 GSTAT
#define MD_GSTAT 0X01 #define MD_GSTAT 0X01
// register 0x30, 0x50 IHOLD_IRUN // register 0x30, 0x50 IHOLD_IRUN
#define MD_IHIR1 0x30 #define MD_IHIR1 0x30
#define MD_IHIR2 0x50 #define MD_IHIR2 0x50
#define MD_IHIR_iHold 0 #define MD_IHIR_iHold 0
#define MD_IHIR_iRun 8 #define MD_IHIR_iRun 8
#define md_IHIR_iHoldDelay 16ul #define md_IHIR_iHoldDelay 16ul
// register 0x6C, 7C CHOPCONF // register 0x6C, 7C CHOPCONF
#define MD_CC1 0X6C #define MD_CC1 0X6C
#define MD_CC2 0X7C #define MD_CC2 0X7C
#define MD_CC_shortProtection 0x40000000 #define MD_CC_shortProtection 0x40000000
#define MD_CC_doubbleEdge 0x20000000 #define MD_CC_doubbleEdge 0x20000000
#define MD_CC_16ustapI 0x10000000 #define MD_CC_16ustapI 0x10000000
#define MD_CC_mres 24 // 4 bits; 1/(2^x / 2^8) microstappen #define MD_CC_mres 24 // 4 bits; 1/(2^x / 2^8) microstappen
#define MD_CC_vsens 0x00020000 #define MD_CC_vsens 0x00020000
#define MD_CC_tbl 15 // 3 bits? #define MD_CC_tbl 15 // 3 bits?
#define MD_CC_cmh BIT14 #define MD_CC_cmh BIT14
#define MD_CC_rndtf 0x00002000 #define MD_CC_rndtf 0x00002000
#define MD_CC_disfdcc 0x00001000 #define MD_CC_disfdcc 0x00001000
#define MD_CC_fd3 BTI11 #define MD_CC_fd3 BTI11
#define MD_CC_hend 7 // 4 bits #define MD_CC_hend 7 // 4 bits
#define MD_CC_hstrt 4 // 3 bits #define MD_CC_hstrt 4 // 3 bits
#define MD_CC_toff 0 // 4 bits #define MD_CC_toff 0 // 4 bits
// bool md_checkError(){ // bool md_checkError(){
// unsigned long stat = md_read(MD_GSTAT); // unsigned long stat = md_read(MD_GSTAT);
// if(stat != 0){ // if(stat != 0){
// if(stat == 0x1){ // only a recet has occert // if(stat == 0x1){ // only a recet has occert
// // restart the motor driver // // restart the motor driver
// md_setup(); // md_setup();
// }else{ // one of the motorst stopt due to short or overheated or a undervoltage in chargepump // }else{ // one of the motorst stopt due to short or overheated or a undervoltage in chargepump
// // wait a while for checking again // // wait a while for checking again
// delay(1000); // delay(1000);
// md_checkError(); // md_checkError();
// } // }
// return true; // return true;
// } // }
// return false; // return false;
// } // }
void MD_write(uchar addr, ulong data) { void MD_write(uchar addr, ulong data) {
char i; char i;
// wait for SPI bus to be available // wait for SPI bus to be available
SPIInitSend(MD_CS, SPI_Mode3); SPIInitSend(MD_CS, SPI_Mode3, SPI_Clock_4MHz);
// set write bit to write // set write bit to write
addr |= 0x80; addr |= 0x80;
SPI_packet[0] = addr; SPI_packet[0] = addr;
// save data to packet buffer // save data to packet buffer
for(i=4; i>0; i--){ for(i=4; i>0; i--){
SPI_packet[i] = data; SPI_packet[i] = data;
data >>= 8; data >>= 8;
} }
SPISend(SPI_Mode3); SPISend(SPI_Mode3);
} }
unsigned long MD_read(uchar addr) { unsigned long MD_read(uchar addr) {
char i; char i;
ulong data; ulong data;
// wait for SPI bus to be available // wait for SPI bus to be available
SPIInitSend(MD_CS, SPI_Mode3); SPIInitSend(MD_CS, SPI_Mode3, SPI_Clock_4MHz);
// set write bit to read // set write bit to read
addr &= ~0x80; addr &= ~0x80;
SPI_packet[0] = addr; SPI_packet[0] = addr;
SPISend(SPI_Mode3); SPISend(SPI_Mode3);
// wait for SPI bus to be available // wait for SPI bus to be available
SPIInitSend(MD_CS, SPI_Mode3); SPIInitSend(MD_CS, SPI_Mode3, SPI_Clock_4MHz);
SPI_packet[0] = addr; SPI_packet[0] = addr;
SPISend(SPI_Mode3); SPISend(SPI_Mode3);
// read data // read data
for(i=2; i<5; i++){ for(i=2; i<5; i++){
data |= (ulong) SPI_packet[i]; data |= (ulong) SPI_packet[i];
data <<= 8; data <<= 8;
} }
return data; return data;
} }
void MDInit(){ void MDInit(){
P1DIR |= MD_CS; // set MD_CS (pin 3) as output P1DIR |= MD_CS; // set MD_CS (pin 3) as output
P1OUT |= MD_CS; // set MD_CS high P1OUT |= MD_CS; // set MD_CS high
MD_write(MD_GCONF, MD_GCONF_stepdir2Enable | MD_GCONF_stepdir1Enable); MD_write(MD_GCONF, MD_GCONF_stepdir2Enable | MD_GCONF_stepdir1Enable);
MD_write(MD_CC1, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | (4ul<<MD_CC_mres) | MD_CC_16ustapI); MD_write(MD_CC1, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | (4ul<<MD_CC_mres) | MD_CC_16ustapI);
MD_write(MD_CC2, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | (4ul<<MD_CC_mres) | MD_CC_16ustapI); MD_write(MD_CC2, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | (4ul<<MD_CC_mres) | MD_CC_16ustapI);
MD_write(MD_IHIR1, 10ul<<MD_IHIR_iHold | 31ul<<MD_IHIR_iRun | 6ul<<md_IHIR_iHoldDelay); MD_write(MD_IHIR1, 10ul<<MD_IHIR_iHold | 31ul<<MD_IHIR_iRun | 6ul<<md_IHIR_iHoldDelay);
MD_write(MD_IHIR2, 10ul<<MD_IHIR_iHold | 31ul<<MD_IHIR_iRun | 6ul<<md_IHIR_iHoldDelay); MD_write(MD_IHIR2, 10ul<<MD_IHIR_iHold | 31ul<<MD_IHIR_iRun | 6ul<<md_IHIR_iHoldDelay);
} }