add frequency option
This commit is contained in:
Mats van Reenen
parent
977c26b2ca
commit
2d38b034ac
155
SPI.c
155
SPI.c
@ -1,65 +1,90 @@
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#include <msp430.h>
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#include "SPI.h"
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uchar SPI_CS;
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int SPIInit(){
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UCA0CTL1 = UCSWRST;
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// setup A0 for SPI
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UCA0CTL0 = SPI_Mode3 | UCMSB | UCMST | (0x10 << 1) | UCSYNC;
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UCA0CTL1 |= UCSSEL_2;
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UCA0BR1 = 0; //TODO: set corect frequency
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UCA0BR0 = 4;
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// config port
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//set SEL to USCI (0b01); MOSI (pin 1), MISO (pin 2), CLK (pin 4)
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P1SEL |= BIT1 | BIT2 | BIT4;
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P1SEL2 |= BIT1 | BIT2 | BIT4;
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UCA0CTL1 &= ~UCSWRST;
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// enable interrupts
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IE2 |= UCA0TXIE;
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IFG2 &= ~UCA0TXIFG;
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// set initial values for vars
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SPI_packetC = 0;
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SPI_CS = 0;
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__enable_interrupt();
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return 0;
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}
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void SPISend(){
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P1OUT &= ~SPI_CS;
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UCA0TXBUF = SPI_packet[SPI_packetC];
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}
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void SPIInitSend(uchar cs, enum SPI_Mode mode){
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while(SPI_CS != 0)
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//TODO: search for a more power effient way for a delay
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__delay_cycles (16000);
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UCA0CTL0 |= mode;
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UCA0CTL0 &= ~mode ^ 0xC0;
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SPI_CS = cs;
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}
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#pragma vector = USCIAB0TX_VECTOR
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__interrupt void ISR_EUSCI_A0(){
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SPI_packet[SPI_packetC] = UCA0RXIFG;
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if(SPI_packetC == 4){
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P1OUT |= SPI_CS;
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SPI_packetC = 0;
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IFG2 &= ~UCA0TXIFG;
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SPI_CS = 0;
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}else{
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SPI_packetC++;
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UCA0TXBUF = SPI_packet[SPI_packetC];
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}
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}
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#include <msp430.h>
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#include "SPI.h"
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uchar SPI_CS = 0;
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int SPIInit(){
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UCA0CTL1 = UCSWRST;
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// setup A0 for SPI
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UCA0CTL0 = UCMSB | UCMST | (0x10 << 1) | UCSYNC;
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UCA0CTL1 |= UCSSEL_2;
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UCA0BR1 = 0;
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UCA0BR0 = 16; // 1 MHz
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// config port
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//set SEL to USCI (0b01); MOSI (pin 1), MISO (pin 2), CLK (pin 4)
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P1SEL |= BIT1 | BIT2 | BIT4;
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P1SEL2 |= BIT1 | BIT2 | BIT4;
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UCA0CTL1 &= ~UCSWRST;
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// enable interrupts
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// IE2 |= UCA0TXIE;
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// IFG2 &= ~UCA0TXIFG;
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// set initial values for vars
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SPI_packetC = 0;
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SPI_CS = 0;
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__enable_interrupt();
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return 0;
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}
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//TODO: add clock freqency configuration
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/*
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* do some configuration before sending the data.
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*
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* @arg uchar cs: the bit of port 1 connected to the chip select pin of target device
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* @arg enum SPI_Mode: the SPI modus (clock pase and polarity)
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* @arg enum SPI_clock: the clock freqency
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*/
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void SPIInitSend(uchar cs, enum SPI_Mode mode, enum SPI_Clock clk){
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//TODO: add a clock as powerefficent delay
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while(SPI_CS != 0); // wait for last transmit to be done
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// set clock frequency
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UCA0BR0 = clk;
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// set SPI mode
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UCA0CTL0 &= 0x3F; // set mode bits to 0
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UCA0CTL0 |= mode;
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// save chip select
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SPI_CS = cs;
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}
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//TODO: make it asyncronily with interupt.
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/*
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* Send the packet stored in SPI_packet. it start from SPI_packetC to the last byte
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*/
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void SPISend(){
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P1OUT &= ~SPI_CS; // select slave
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while(SPI_packetC < 5){
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// send one byte
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UCA0TXBUF = SPI_packet[SPI_packetC];
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//TODO: fix the delay! it's to short with low data speeds
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if(UCA0BR0 > 4)
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// if de frequency lower than 4 MHz do a manual delay. this is a workaround for the to short delay
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// this works down to 1 MHz
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__delay_cycles(129);
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else
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while(UCB0STAT & UCBUSY); // wait for SPI TX/RX to finish
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// save recieved data
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SPI_packet[SPI_packetC] = UCA0RXIFG;
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// increase counter for next byte
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SPI_packetC++;
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}
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SPI_packetC = 0; // recet counter
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P1OUT |= SPI_CS; // deselect slave
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SPI_CS = 0;
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}
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45
SPI.h
45
SPI.h
@ -1,22 +1,23 @@
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/*
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* SPI.c
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*
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* Created on: 4 mei 2020
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* Author: mreenen
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*/
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#ifndef SPI_C_
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#define SPI_C_
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#include "typedefExtention.h"
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enum SPI_Mode {SPI_Mode0=0b00<<6, SPI_Mode1=0b10<<6, SPI_Mode2=0b11<<6, SPI_Mode3=0b01<<6};
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uchar SPI_packet[5];
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char SPI_packetC;
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int SPIInit();
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void SPISend();
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void SPIInitSend(uchar cs, enum SPI_Mode mode);
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#endif /* SPI_C_ */
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/*
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* SPI.c
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*
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* Created on: 4 mei 2020
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* Author: mreenen
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*/
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#ifndef SPI_C_
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#define SPI_C_
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#include "typedefExtention.h"
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enum SPI_Mode {SPI_Mode0=0b00<<6, SPI_Mode1=0b10<<6, SPI_Mode2=0b11<<6, SPI_Mode3=0b01<<6};
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enum SPI_Clock {SPI_Clock_1MHz=16, SPI_Clock_2MHz=8, SPI_Clock_4MHz=4, SPI_Clock_8MHz=2};
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uchar SPI_packet[5];
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char SPI_packetC;
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int SPIInit();
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void SPISend();
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void SPIInitSend(uchar cs, enum SPI_Mode mode, enum SPI_Clock clk);
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#endif /* SPI_C_ */
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@ -88,7 +88,7 @@ void MC_write(uchar addr, ulong data) {
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char i;
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// wait for SPI bus to be available
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SPIInitSend(MC_CS, SPI_Mode3);
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SPIInitSend(MC_CS, SPI_Mode3, SPI_Clock_1MHz);
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// set write bit to write
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addr &= ~0x01;
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@ -109,7 +109,7 @@ ulong MC_read(unsigned char addr) {
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ulong data;
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// wait for SPI bus to be available
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SPIInitSend(MC_CS, SPI_Mode3);
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SPIInitSend(MC_CS, SPI_Mode3, SPI_Clock_1MHz);
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// set write bit to read
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addr |= 0x01;
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@ -119,7 +119,7 @@ ulong MC_read(unsigned char addr) {
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SPISend();
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// wait for SPI bus to be available
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SPIInitSend(MC_CS, SPI_Mode3);
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SPIInitSend(MC_CS, SPI_Mode3, SPI_Clock_1MHz);
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// set write bit to read
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addr |= 0x01;
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248
motorDriver.c
248
motorDriver.c
@ -1,124 +1,124 @@
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/*
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* motorDriver.c
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*
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* Created on: 4 mei 2020
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* Author: mreenen
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*/
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#include <msp430.h>
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#include "typedefExtention.h"
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#include "SPI.h"
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#include "motorDriver.h"
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const uchar MD_CS = BIT3;
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// register 0x00 GCINF
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#define MD_GCONF 0X00
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#define MD_GCONF_singgelMotor 0x00000001
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#define MD_GCONF_stepdir1Enable 0x00000002
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#define MD_GCONF_stepdir2Enable 0x00000004
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#define MD_GCONF_motor1Revers 0x00000010
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#define MD_GCONF_motor1Revers 0x00000010
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#define MD_GCONF_lockGCONF 0x00000020
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// register 0x01 GSTAT
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#define MD_GSTAT 0X01
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// register 0x30, 0x50 IHOLD_IRUN
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#define MD_IHIR1 0x30
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#define MD_IHIR2 0x50
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#define MD_IHIR_iHold 0
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#define MD_IHIR_iRun 8
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#define md_IHIR_iHoldDelay 16ul
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// register 0x6C, 7C CHOPCONF
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#define MD_CC1 0X6C
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#define MD_CC2 0X7C
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#define MD_CC_shortProtection 0x40000000
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#define MD_CC_doubbleEdge 0x20000000
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#define MD_CC_16ustapI 0x10000000
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#define MD_CC_mres 24 // 4 bits; 1/(2^x / 2^8) microstappen
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#define MD_CC_vsens 0x00020000
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#define MD_CC_tbl 15 // 3 bits?
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#define MD_CC_cmh BIT14
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#define MD_CC_rndtf 0x00002000
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#define MD_CC_disfdcc 0x00001000
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#define MD_CC_fd3 BTI11
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#define MD_CC_hend 7 // 4 bits
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#define MD_CC_hstrt 4 // 3 bits
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#define MD_CC_toff 0 // 4 bits
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// bool md_checkError(){
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// unsigned long stat = md_read(MD_GSTAT);
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// if(stat != 0){
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// if(stat == 0x1){ // only a recet has occert
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// // restart the motor driver
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// md_setup();
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// }else{ // one of the motorst stopt due to short or overheated or a undervoltage in chargepump
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// // wait a while for checking again
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// delay(1000);
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// md_checkError();
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// }
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// return true;
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// }
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// return false;
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// }
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void MD_write(uchar addr, ulong data) {
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char i;
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// wait for SPI bus to be available
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SPIInitSend(MD_CS, SPI_Mode3);
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// set write bit to write
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addr |= 0x80;
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SPI_packet[0] = addr;
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// save data to packet buffer
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for(i=4; i>0; i--){
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SPI_packet[i] = data;
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data >>= 8;
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}
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SPISend(SPI_Mode3);
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}
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unsigned long MD_read(uchar addr) {
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char i;
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ulong data;
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// wait for SPI bus to be available
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SPIInitSend(MD_CS, SPI_Mode3);
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// set write bit to read
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addr &= ~0x80;
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SPI_packet[0] = addr;
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SPISend(SPI_Mode3);
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// wait for SPI bus to be available
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SPIInitSend(MD_CS, SPI_Mode3);
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SPI_packet[0] = addr;
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SPISend(SPI_Mode3);
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// read data
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for(i=2; i<5; i++){
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data |= (ulong) SPI_packet[i];
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data <<= 8;
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}
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return data;
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}
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void MDInit(){
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P1DIR |= MD_CS; // set MD_CS (pin 3) as output
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P1OUT |= MD_CS; // set MD_CS high
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MD_write(MD_GCONF, MD_GCONF_stepdir2Enable | MD_GCONF_stepdir1Enable);
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MD_write(MD_CC1, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | (4ul<<MD_CC_mres) | MD_CC_16ustapI);
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MD_write(MD_CC2, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | (4ul<<MD_CC_mres) | MD_CC_16ustapI);
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MD_write(MD_IHIR1, 10ul<<MD_IHIR_iHold | 31ul<<MD_IHIR_iRun | 6ul<<md_IHIR_iHoldDelay);
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MD_write(MD_IHIR2, 10ul<<MD_IHIR_iHold | 31ul<<MD_IHIR_iRun | 6ul<<md_IHIR_iHoldDelay);
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}
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/*
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* motorDriver.c
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*
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* Created on: 4 mei 2020
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* Author: mreenen
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*/
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#include <msp430.h>
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#include "typedefExtention.h"
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#include "SPI.h"
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#include "motorDriver.h"
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const uchar MD_CS = BIT3;
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// register 0x00 GCINF
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#define MD_GCONF 0X00
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#define MD_GCONF_singgelMotor 0x00000001
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#define MD_GCONF_stepdir1Enable 0x00000002
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#define MD_GCONF_stepdir2Enable 0x00000004
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#define MD_GCONF_motor1Revers 0x00000010
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#define MD_GCONF_motor1Revers 0x00000010
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#define MD_GCONF_lockGCONF 0x00000020
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// register 0x01 GSTAT
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#define MD_GSTAT 0X01
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// register 0x30, 0x50 IHOLD_IRUN
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#define MD_IHIR1 0x30
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#define MD_IHIR2 0x50
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#define MD_IHIR_iHold 0
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#define MD_IHIR_iRun 8
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#define md_IHIR_iHoldDelay 16ul
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// register 0x6C, 7C CHOPCONF
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#define MD_CC1 0X6C
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#define MD_CC2 0X7C
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#define MD_CC_shortProtection 0x40000000
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#define MD_CC_doubbleEdge 0x20000000
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#define MD_CC_16ustapI 0x10000000
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#define MD_CC_mres 24 // 4 bits; 1/(2^x / 2^8) microstappen
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#define MD_CC_vsens 0x00020000
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#define MD_CC_tbl 15 // 3 bits?
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#define MD_CC_cmh BIT14
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#define MD_CC_rndtf 0x00002000
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#define MD_CC_disfdcc 0x00001000
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#define MD_CC_fd3 BTI11
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#define MD_CC_hend 7 // 4 bits
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#define MD_CC_hstrt 4 // 3 bits
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#define MD_CC_toff 0 // 4 bits
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// bool md_checkError(){
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// unsigned long stat = md_read(MD_GSTAT);
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// if(stat != 0){
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// if(stat == 0x1){ // only a recet has occert
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// // restart the motor driver
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// md_setup();
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// }else{ // one of the motorst stopt due to short or overheated or a undervoltage in chargepump
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// // wait a while for checking again
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// delay(1000);
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// md_checkError();
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// }
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// return true;
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// }
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// return false;
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// }
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void MD_write(uchar addr, ulong data) {
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char i;
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// wait for SPI bus to be available
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SPIInitSend(MD_CS, SPI_Mode3, SPI_Clock_4MHz);
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// set write bit to write
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addr |= 0x80;
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SPI_packet[0] = addr;
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// save data to packet buffer
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for(i=4; i>0; i--){
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SPI_packet[i] = data;
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data >>= 8;
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}
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SPISend(SPI_Mode3);
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}
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unsigned long MD_read(uchar addr) {
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char i;
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ulong data;
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// wait for SPI bus to be available
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SPIInitSend(MD_CS, SPI_Mode3, SPI_Clock_4MHz);
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// set write bit to read
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addr &= ~0x80;
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SPI_packet[0] = addr;
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SPISend(SPI_Mode3);
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// wait for SPI bus to be available
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SPIInitSend(MD_CS, SPI_Mode3, SPI_Clock_4MHz);
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SPI_packet[0] = addr;
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SPISend(SPI_Mode3);
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// read data
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for(i=2; i<5; i++){
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data |= (ulong) SPI_packet[i];
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data <<= 8;
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}
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return data;
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}
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void MDInit(){
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P1DIR |= MD_CS; // set MD_CS (pin 3) as output
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P1OUT |= MD_CS; // set MD_CS high
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MD_write(MD_GCONF, MD_GCONF_stepdir2Enable | MD_GCONF_stepdir1Enable);
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MD_write(MD_CC1, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | (4ul<<MD_CC_mres) | MD_CC_16ustapI);
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MD_write(MD_CC2, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | (4ul<<MD_CC_mres) | MD_CC_16ustapI);
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MD_write(MD_IHIR1, 10ul<<MD_IHIR_iHold | 31ul<<MD_IHIR_iRun | 6ul<<md_IHIR_iHoldDelay);
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MD_write(MD_IHIR2, 10ul<<MD_IHIR_iHold | 31ul<<MD_IHIR_iRun | 6ul<<md_IHIR_iHoldDelay);
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}
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